URL
https://opencores.org/ocsvn/sport/sport/trunk
[/] [sport/] [trunk/] [sim/] [compile_hw.do.bak] - Blame information for rev 5
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
5 |
jeaander |
# hardware
|
2 |
|
|
vlog -work work +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v
|
3 |
|
|
vlog -work work +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/fifos.v
|
4 |
|
|
vlog -work work +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v
|
5 |
|
|
|
6 |
|
|
# testbench stuff
|
7 |
|
|
vlog -work work +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/bench C:/Users/jeffA/Desktop/rtl/sport/trunk/bench/testbench_top.v
|
8 |
|
|
vlog -work work +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/bench +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog C:/Users/jeffA/Desktop/rtl/sport/trunk/bench/testcase.v
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.