| 1 |
7 |
jeaander |
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1424458777611 ""}
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| 2 |
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Design Assistant Quartus II 64-Bit " "Running Quartus II 64-Bit Design Assistant" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 14.0.0 Build 200 06/17/2014 SJ Web Edition " "Version 14.0.0 Build 200 06/17/2014 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1424458777611 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 20 13:59:37 2015 " "Processing started: Fri Feb 20 13:59:37 2015" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1424458777611 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Assistant" 0 -1 1424458777611 ""}
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| 3 |
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_drc --read_settings_files=off --write_settings_files=off sport_top -c sport_top " "Command: quartus_drc --read_settings_files=off --write_settings_files=off sport_top -c sport_top" { } { } 0 0 "Command: %1!s!" 0 0 "Design Assistant" 0 -1 1424458777611 ""}
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| 4 |
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{ "Info" "IMPP_MPP_USER_DEVICE" "sport_top EP4CGX15BF14C6 " "Selected device EP4CGX15BF14C6 for design \"sport_top\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Design Assistant" 0 -1 1424458777673 ""}
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| 5 |
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{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "sport_top.sdc " "Synopsys Design Constraints File file not found: 'sport_top.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Design Assistant" 0 -1 1424458778500 ""}
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| 6 |
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{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Design Assistant" 0 -1 1424458778500 ""}
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| 7 |
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{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Design Assistant" 0 -1 1424458778516 ""}
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| 8 |
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{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Design Assistant" 0 -1 1424458778516 ""}
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| 9 |
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{ "Critical Warning" "WDRC_NO_SYNZER_IN_ASYNC_CLK_DOMAIN" "Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains 2 16 " "(High) Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains. (Value defined:2). Found 16 asynchronous clock domain interface structure(s) related to this rule." { { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[7\] " "Node \"wb_interface_sport:wb_interface\|txreg\[7\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 202 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[6\] " "Node \"wb_interface_sport:wb_interface\|txreg\[6\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 203 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[4\] " "Node \"wb_interface_sport:wb_interface\|txreg\[4\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 205 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[5\] " "Node \"wb_interface_sport:wb_interface\|txreg\[5\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 204 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[2\] " "Node \"wb_interface_sport:wb_interface\|txreg\[2\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 207 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[3\] " "Node \"wb_interface_sport:wb_interface\|txreg\[3\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 206 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[1\] " "Node \"wb_interface_sport:wb_interface\|txreg\[1\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 208 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[0\] " "Node \"wb_interface_sport:wb_interface\|txreg\[0\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 209 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[9\] " "Node \"wb_interface_sport:wb_interface\|txreg\[9\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 200 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[8\] " "Node \"wb_interface_sport:wb_interface\|txreg\[8\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 201 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[13\] " "Node \"wb_interface_sport:wb_interface\|txreg\[13\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 196 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[12\] " "Node \"wb_interface_sport:wb_interface\|txreg\[12\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 197 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[11\] " "Node \"wb_interface_sport:wb_interface\|txreg\[11\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 198 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[10\] " "Node \"wb_interface_sport:wb_interface\|txreg\[10\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 199 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[14\] " "Node \"wb_interface_sport:wb_interface\|txreg\[14\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 195 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[16\] " "Node \"wb_interface_sport:wb_interface\|txreg\[16\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 194 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} } { } 1 308060 "(High) %1!s!. (Value defined:%2!d!). Found %3!d! asynchronous clock domain interface structure(s) related to this rule." 0 0 "Design Assistant" 0 -1 1424458778672 ""}
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| 10 |
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{ "Critical Warning" "WDRC_IMPROPER_SYNZER_IN_ASYNC_CLK_DOMAIN" "Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains 2 15 " "(High) Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains. (Value defined:2). Found 15 asynchronous clock domain interface structure(s) related to this rule." { { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[7\] " "Node \"wb_interface_sport:wb_interface\|txreg\[7\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 202 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[6\] " "Node \"wb_interface_sport:wb_interface\|txreg\[6\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 203 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[4\] " "Node \"wb_interface_sport:wb_interface\|txreg\[4\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 205 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[5\] " "Node \"wb_interface_sport:wb_interface\|txreg\[5\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 204 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[2\] " "Node \"wb_interface_sport:wb_interface\|txreg\[2\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 207 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[3\] " "Node \"wb_interface_sport:wb_interface\|txreg\[3\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 206 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[1\] " "Node \"wb_interface_sport:wb_interface\|txreg\[1\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 208 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[0\] " "Node \"wb_interface_sport:wb_interface\|txreg\[0\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 209 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[9\] " "Node \"wb_interface_sport:wb_interface\|txreg\[9\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 200 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[8\] " "Node \"wb_interface_sport:wb_interface\|txreg\[8\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 201 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[13\] " "Node \"wb_interface_sport:wb_interface\|txreg\[13\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 196 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[12\] " "Node \"wb_interface_sport:wb_interface\|txreg\[12\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 197 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[11\] " "Node \"wb_interface_sport:wb_interface\|txreg\[11\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 198 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[10\] " "Node \"wb_interface_sport:wb_interface\|txreg\[10\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 199 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wb_interface_sport:wb_interface\|txreg\[14\] " "Node \"wb_interface_sport:wb_interface\|txreg\[14\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 195 9684 10422 0} } } } } 1 308012 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} } { } 1 308067 "(High) %1!s!. (Value defined:%2!d!). Found %3!d! asynchronous clock domain interface structure(s) related to this rule." 0 0 "Design Assistant" 0 -1 1424458778672 ""}
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| 11 |
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{ "Warning" "WDRC_EXTERNAL_RESET" "Rule R102: External reset signals should be synchronized using two cascaded registers 1 " "(Medium) Rule R102: External reset signals should be synchronized using two cascaded registers. Found 1 node(s) related to this rule." { { "Warning" "WDRC_NODES_WARNING" " wb_rst_i " "Node \"wb_rst_i\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 99 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 179 9684 10422 0} } } } } 0 308010 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778672 ""} } { } 0 308023 "(Medium) %1!s!. Found %2!d! node(s) related to this rule." 0 0 "Design Assistant" 0 -1 1424458778672 ""}
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| 12 |
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{ "Warning" "WDRC_SYNZER_IN_ALL_SIGNAL_BTW_ASYNC_CLK_DOMAIN" "Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain 2 1 " "(Medium) Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain. (Value defined:2). Found 1 asynchronous clock domain interface structure(s) related to this rule." { { "Warning" "WDRC_NODES_WARNING" " wb_interface_sport:wb_interface\|txreg (Bus) " "Node \"wb_interface_sport:wb_interface\|txreg (Bus)\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 202 9684 10422 0} } } } } 0 308010 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} } { } 0 308071 "(Medium) %1!s!. (Value defined:%2!d!). Found %3!d! asynchronous clock domain interface structure(s) related to this rule." 0 0 "Design Assistant" 0 -1 1424458778687 ""}
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| 13 |
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{ "Info" "IDRC_HIGH_FANOUT" "Rule T101: Nodes with more than the specified number of fan-outs 30 1 " "(Information) Rule T101: Nodes with more than the specified number of fan-outs. (Value defined:30). Found 1 node(s) with highest fan-out." { { "Info" "IDRC_NODES_INFO" " wb_interface_sport:wb_interface\|wb_dat_o~31 " "Node \"wb_interface_sport:wb_interface\|wb_dat_o~31\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 107 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 256 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} } { } 0 308046 "(Information) %1!s!. (Value defined:%2!d!). Found %3!d! node(s) with highest fan-out." 0 0 "Design Assistant" 0 -1 1424458778687 ""}
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| 14 |
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{ "Info" "IDRC_TOP_FANOUT" "Rule T102: Top nodes with the highest number of fan-outs 50 50 " "(Information) Rule T102: Top nodes with the highest number of fan-outs. (Value defined:50). Found 50 node(s) with highest fan-out." { { "Info" "IDRC_NODES_INFO" " wb_interface_sport:wb_interface\|wb_dat_o~31 " "Node \"wb_interface_sport:wb_interface\|wb_dat_o~31\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 107 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 256 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " wb_interface_sport:wb_interface\|always4~1 " "Node \"wb_interface_sport:wb_interface\|always4~1\"" { } { { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 251 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " state.010 " "Node \"state.010\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 118 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 231 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " txsampleCnt_tx\[1\] " "Node \"txsampleCnt_tx\[1\]\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 276 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 219 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " txsampleCnt_tx\[0\] " "Node \"txsampleCnt_tx\[0\]\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 276 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 220 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " txpacketCnt_tx\[4\] " "Node \"txpacketCnt_tx\[4\]\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 285 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 226 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " wb_interface_sport:wb_interface\|Equal1~0 " "Node \"wb_interface_sport:wb_interface\|Equal1~0\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 207 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 249 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " txpacketCnt_tx\[2\] " "Node \"txpacketCnt_tx\[2\]\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 285 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 228 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " wb_interface_sport:wb_interface\|always3~1 " "Node \"wb_interface_sport:wb_interface\|always3~1\"" { } { { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 253 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " txpacketCnt_tx\[3\] " "Node \"txpacketCnt_tx\[3\]\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 285 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 227 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " txpacketCnt_tx\[7\] " "Node \"txpacketCnt_tx\[7\]\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 285 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 223 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " txpacketCnt_tx\[8\] " "Node \"txpacketCnt_tx\[8\]\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 285 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 222 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " Equal0~1 " "Node \"Equal0~1\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 265 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 261 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " Equal1~5 " "Node \"Equal1~5\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 266 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 269 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " txpacketCnt_tx\[5\] " "Node \"txpacketCnt_tx\[5\]\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 285 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 225 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " Selector1~0 " "Node \"Selector1~0\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 252 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 263 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " txpacketCnt_tx\[6\] " "Node \"txpacketCnt_tx\[6\]\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 285 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 224 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " state.011 " "Node \"state.011\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 118 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 237 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " Equal1~0 " "Node \"Equal1~0\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 266 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 264 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " Equal0~2 " "Node \"Equal0~2\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 265 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 262 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " tx_start_tx " "Node \"tx_start_tx\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 152 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 239 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " Equal0~0 " "Node \"Equal0~0\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 265 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 260 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " state.001 " "Node \"state.001\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 118 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 230 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " wb_interface_sport:wb_interface\|txreg\[0\] " "Node \"wb_interface_sport:wb_interface\|txreg\[0\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 209 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " txpacketCnt_tx\[9\] " "Node \"txpacketCnt_tx\[9\]\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 285 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 221 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " wb_dat_i\[10\] " "Node \"wb_dat_i\[10\]\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 100 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 107 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " wb_interface_sport:wb_interface\|txreg\[3\] " "Node \"wb_interface_sport:wb_interface\|txreg\[3\]\"" { } { { "../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v" 203 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 206 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " Selector1~1 " "Node \"Selector1~1\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 252 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 273 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " wb_rst_i " "Node \"wb_rst_i\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 99 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 179 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_NODES_INFO" " wb_dat_i\[13\] " "Node \"wb_dat_i\[13\]\"" { } { { "../../rtl/verilog/sport_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v" 100 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/altera/" { { 0 { 0 ""} 0 110 9684 10422 0} } } } } 0 308011 "Node %1!s! \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424458778687 ""} { "Info" "IDRC_REPORT_TRUNCATE_MESSAGE" "30 " "Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated." { } { } 0 308002 "Truncated list of Design Assistant messages to %1!d! messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated." 0 0 "Quartus II" 0 -1 1424458778687 ""} } { } 0 308044 "(Information) %1!s!. (Value defined:%2!d!). Found %3!d! node(s) with highest fan-out." 0 0 "Design Assistant" 0 -1 1424458778687 ""}
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| 15 |
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{ "Info" "IDRC_REPORT_HEALTH_POST_SYNTHESIS" "51 33 " "Design Assistant information: finished post-synthesis analysis of current design -- generated 51 information messages and 33 warning messages" { } { } 2 308006 "Design Assistant information: finished post-synthesis analysis of current design -- generated %1!d! information messages and %2!d! warning messages" 0 0 "Design Assistant" 0 -1 1424458778687 ""}
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| 16 |
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{ "Info" "IQEXE_ERROR_COUNT" "Design Assistant 0 s 38 s Quartus II 64-Bit " "Quartus II 64-Bit Design Assistant was successful. 0 errors, 38 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "474 " "Peak virtual memory: 474 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1424458778765 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 20 13:59:38 2015 " "Processing ended: Fri Feb 20 13:59:38 2015" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1424458778765 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1424458778765 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1424458778765 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Assistant" 0 -1 1424458778765 ""}
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