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[/] [sport/] [trunk/] [syn/] [altera/] [output_files/] [sport_top.flow.rpt] - Blame information for rev 7

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Line No. Rev Author Line
1 7 jeaander
Flow report for sport_top
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Fri Feb 20 13:59:44 2015
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Quartus II 64-Bit Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
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---------------------
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; Table of Contents ;
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---------------------
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  1. Legal Notice
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  2. Flow Summary
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  3. Flow Settings
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  4. Flow Non-Default Global Settings
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  5. Flow Elapsed Time
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  6. Flow OS Summary
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  7. Flow Log
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  8. Flow Messages
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  9. Flow Suppressed Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, the Altera Quartus II License Agreement,
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the Altera MegaCore Function License Agreement, or other
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applicable license agreement, including, without limitation,
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that your use is for the sole purpose of programming logic
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devices manufactured by Altera and sold by Altera or its
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authorized distributors.  Please refer to the applicable
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agreement for further details.
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+---------------------------------------------------------------------------------+
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; Flow Summary                                                                    ;
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+------------------------------------+--------------------------------------------+
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; Flow Status                        ; Flow Failed - Fri Feb 20 13:59:44 2015     ;
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; Quartus II 64-Bit Version          ; 14.0.0 Build 200 06/17/2014 SJ Web Edition ;
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; Revision Name                      ; sport_top                                  ;
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; Top-level Entity Name              ; sport_top                                  ;
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; Family                             ; Cyclone IV GX                              ;
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; Device                             ; EP4CGX15BF14C6                             ;
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; Timing Models                      ; Final                                      ;
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; Total logic elements               ; 61                                         ;
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;     Total combinational functions  ; 38 / 14,400 ( < 1 % )                      ;
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;     Dedicated logic registers      ; 39 / 14,400 ( < 1 % )                      ;
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; Total registers                    ; 39                                         ;
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; Total pins                         ; 89 / 81 ( 110 % )                          ;
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; Total virtual pins                 ; 0                                          ;
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; Total memory bits                  ; 0 / 552,960 ( 0 % )                        ;
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; Embedded Multiplier 9-bit elements ; 0                                          ;
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; Total GXB Receiver Channel PCS     ; 0 / 2 ( 0 % )                              ;
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; Total GXB Receiver Channel PMA     ; 0 / 2 ( 0 % )                              ;
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; Total GXB Transmitter Channel PCS  ; 0 / 2 ( 0 % )                              ;
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; Total GXB Transmitter Channel PMA  ; 0 / 2 ( 0 % )                              ;
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; Total PLLs                         ; 0 / 3 ( 0 % )                              ;
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+------------------------------------+--------------------------------------------+
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+-----------------------------------------+
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; Flow Settings                           ;
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+-------------------+---------------------+
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; Option            ; Setting             ;
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+-------------------+---------------------+
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; Start date & time ; 02/20/2015 13:59:33 ;
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; Main task         ; Compilation         ;
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; Revision Name     ; sport_top           ;
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+-------------------+---------------------+
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+---------------------------------------------------------------------------------------------------------------------+
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; Flow Non-Default Global Settings                                                                                    ;
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+-------------------------------------+--------------------------------+---------------+-------------+----------------+
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; Assignment Name                     ; Value                          ; Default Value ; Entity Name ; Section Id     ;
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+-------------------------------------+--------------------------------+---------------+-------------+----------------+
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; COMPILER_SIGNATURE_ID               ; 61959091049986.142445877304824 ; --            ; --          ; --             ;
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; EDA_OUTPUT_DATA_FORMAT              ; Verilog Hdl                    ; --            ; --          ; eda_simulation ;
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; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (Verilog)      ;         ; --          ; --             ;
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; MAX_CORE_JUNCTION_TEMP              ; 85                             ; --            ; --          ; --             ;
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; MIN_CORE_JUNCTION_TEMP              ; 0                              ; --            ; --          ; --             ;
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; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                           ; --            ; --          ; --             ;
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; PARTITION_COLOR                     ; 16764057                       ; --            ; --          ; Top            ;
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; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING          ; --            ; --          ; Top            ;
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; PARTITION_NETLIST_TYPE              ; SOURCE                         ; --            ; --          ; Top            ;
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; PROJECT_OUTPUT_DIRECTORY            ; output_files                   ; --            ; --          ; --             ;
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+-------------------------------------+--------------------------------+---------------+-------------+----------------+
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+-----------------------------------------------------------------------------------------------------------------------------+
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; Flow Elapsed Time                                                                                                           ;
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+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Module Name             ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
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+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Analysis & Synthesis    ; 00:00:02     ; 1.0                     ; 571 MB              ; 00:00:02                           ;
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; Design Assistant        ; 00:00:01     ; 1.0                     ; 474 MB              ; 00:00:01                           ;
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; I/O Assignment Analysis ; 00:00:02     ; 1.0                     ; 663 MB              ; 00:00:02                           ;
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; Total                   ; 00:00:05     ; --                      ; --                  ; 00:00:05                           ;
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+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
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+--------------------------------------------------------------------------------------+
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; Flow OS Summary                                                                      ;
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+-------------------------+------------------+-----------+------------+----------------+
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; Module Name             ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
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+-------------------------+------------------+-----------+------------+----------------+
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; Analysis & Synthesis    ; jeffA-PC         ; Windows 7 ; 6.1        ; x86_64         ;
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; Design Assistant        ; jeffA-PC         ; Windows 7 ; 6.1        ; x86_64         ;
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; I/O Assignment Analysis ; jeffA-PC         ; Windows 7 ; 6.1        ; x86_64         ;
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+-------------------------+------------------+-----------+------------+----------------+
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------------
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; Flow Log ;
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------------
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quartus_map --read_settings_files=on --write_settings_files=off sport_top -c sport_top
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quartus_drc --read_settings_files=off --write_settings_files=off sport_top -c sport_top
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quartus_fit --read_settings_files=on --write_settings_files=off sport_top -c sport_top --floorplan
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