1 |
7 |
jeaander |
# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
|
2 |
|
|
# Your use of Altera Corporation's design tools, logic functions
|
3 |
|
|
# and other software and tools, and its AMPP partner logic
|
4 |
|
|
# functions, and any output files from any of the foregoing
|
5 |
|
|
# (including device programming or simulation files), and any
|
6 |
|
|
# associated documentation or information are expressly subject
|
7 |
|
|
# to the terms and conditions of the Altera Program License
|
8 |
|
|
# Subscription Agreement, the Altera Quartus II License Agreement,
|
9 |
|
|
# the Altera MegaCore Function License Agreement, or other
|
10 |
|
|
# applicable license agreement, including, without limitation,
|
11 |
|
|
# that your use is for the sole purpose of programming logic
|
12 |
|
|
# devices manufactured by Altera and sold by Altera or its
|
13 |
|
|
# authorized distributors. Please refer to the applicable
|
14 |
|
|
# agreement for further details.
|
15 |
|
|
|
16 |
|
|
# Quartus II: Generate Tcl File for Project
|
17 |
|
|
# File: sport_top.tcl
|
18 |
|
|
# Generated on: Fri Feb 20 13:49:57 2015
|
19 |
|
|
|
20 |
|
|
# Load Quartus II Tcl Project package
|
21 |
|
|
package require ::quartus::project
|
22 |
|
|
|
23 |
|
|
set need_to_close_project 0
|
24 |
|
|
set make_assignments 1
|
25 |
|
|
|
26 |
|
|
# Check that the right project is open
|
27 |
|
|
if {[is_project_open]} {
|
28 |
|
|
if {[string compare $quartus(project) "sport_top"]} {
|
29 |
|
|
puts "Project sport_top is not open"
|
30 |
|
|
set make_assignments 0
|
31 |
|
|
}
|
32 |
|
|
} else {
|
33 |
|
|
# Only open if not already open
|
34 |
|
|
if {[project_exists sport_top]} {
|
35 |
|
|
project_open -revision sport_top sport_top
|
36 |
|
|
} else {
|
37 |
|
|
project_new -revision sport_top sport_top
|
38 |
|
|
}
|
39 |
|
|
set need_to_close_project 1
|
40 |
|
|
}
|
41 |
|
|
|
42 |
|
|
# Make assignments
|
43 |
|
|
if {$make_assignments} {
|
44 |
|
|
set_global_assignment -name FAMILY "Cyclone IV GX"
|
45 |
|
|
set_global_assignment -name DEVICE EP4CGX15BF14C6
|
46 |
|
|
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
|
47 |
|
|
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:24:50 FEBRUARY 20, 2015"
|
48 |
|
|
set_global_assignment -name LAST_QUARTUS_VERSION 14.0
|
49 |
|
|
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/wb_interface.v
|
50 |
|
|
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/sport_top.v
|
51 |
|
|
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/sport_defines.v
|
52 |
|
|
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/fifos.v
|
53 |
|
|
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
54 |
|
|
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
55 |
|
|
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
56 |
|
|
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
|
57 |
|
|
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 169
|
58 |
|
|
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
|
59 |
|
|
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
60 |
|
|
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
|
61 |
|
|
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
|
62 |
|
|
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
|
63 |
|
|
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
|
64 |
|
|
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
65 |
|
|
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
66 |
|
|
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
67 |
|
|
set_location_assignment IOBANK_3 -to wb_dat_o[0]
|
68 |
|
|
set_location_assignment IOBANK_3 -to DRxPRI
|
69 |
|
|
set_location_assignment IOBANK_3A -to DRxSEC
|
70 |
|
|
set_location_assignment IOBANK_4 -to DTxPRI
|
71 |
|
|
set_location_assignment IOBANK_6 -to DTxSEC
|
72 |
|
|
set_location_assignment IOBANK_6 -to RSCLKx
|
73 |
|
|
set_location_assignment IOBANK_7 -to TFSx
|
74 |
|
|
set_location_assignment IOBANK_8 -to TRSx
|
75 |
|
|
set_location_assignment PIN_B11 -to TSCLKx
|
76 |
|
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
77 |
|
|
|
78 |
|
|
# Commit assignments
|
79 |
|
|
export_assignments
|
80 |
|
|
|
81 |
|
|
# Close project
|
82 |
|
|
if {$need_to_close_project} {
|
83 |
|
|
project_close
|
84 |
|
|
}
|
85 |
|
|
}
|