URL
https://opencores.org/ocsvn/sport/sport/trunk
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
7 |
jeaander |
Release 14.7 - ngc2edif P.20131013 (nt64)
|
2 |
|
|
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
3 |
|
|
Reading design sport_top.ngc ...
|
4 |
|
|
WARNING:NetListWriters:298 - No output is written to sport_top.xncf, ignored.
|
5 |
|
|
Processing design ...
|
6 |
|
|
Preping design's networks ...
|
7 |
|
|
Preping design's macros ...
|
8 |
|
|
WARNING:NetListWriters:306 - Signal bus wb_interface/rxreg<20 : 0> on block
|
9 |
|
|
sport_top is not reconstructed, because there are some missing bus signals.
|
10 |
|
|
WARNING:NetListWriters:306 - Signal bus wb_interface/txreg<20 : 0> on block
|
11 |
|
|
sport_top is not reconstructed, because there are some missing bus signals.
|
12 |
|
|
finished :Prep
|
13 |
|
|
Writing EDIF netlist file sport_top.edif ...
|
14 |
|
|
ngc2edif: Total memory usage is 79372 kilobytes
|
15 |
|
|
|
16 |
|
|
Release 14.7 - ngc2edif P.20131013 (nt64)
|
17 |
|
|
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
18 |
|
|
Reading design sport_top.ngc ...
|
19 |
|
|
WARNING:NetListWriters:298 - No output is written to sport_top.xncf, ignored.
|
20 |
|
|
Processing design ...
|
21 |
|
|
Preping design's networks ...
|
22 |
|
|
Preping design's macros ...
|
23 |
|
|
WARNING:NetListWriters:306 - Signal bus wb_interface/rxreg<20 : 0> on block
|
24 |
|
|
sport_top is not reconstructed, because there are some missing bus signals.
|
25 |
|
|
WARNING:NetListWriters:306 - Signal bus wb_interface/txreg<20 : 0> on block
|
26 |
|
|
sport_top is not reconstructed, because there are some missing bus signals.
|
27 |
|
|
finished :Prep
|
28 |
|
|
Writing EDIF netlist file sport_top.edif ...
|
29 |
|
|
ngc2edif: Total memory usage is 79052 kilobytes
|
30 |
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.