| 1 |
7 |
jeaander |
|
| 2 |
|
|
****** PlanAhead v14.7 (64-bit)
|
| 3 |
|
|
**** Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013
|
| 4 |
|
|
** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
|
| 5 |
|
|
|
| 6 |
|
|
INFO: [Common 17-78] Attempting to get a license: PlanAhead
|
| 7 |
|
|
INFO: [Common 17-290] Got license for PlanAhead
|
| 8 |
|
|
INFO: [Device 21-36] Loading parts and site information from C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
|
| 9 |
|
|
Parsing RTL primitives file [C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
|
| 10 |
|
|
Finished parsing RTL primitives file [C:/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
|
| 11 |
|
|
start_gui
|
| 12 |
|
|
source C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/ise/sport_top/pa.fromNetlist.tcl
|
| 13 |
|
|
# create_project -name sport_top -dir "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/ise/sport_top/planAhead_run_2" -part xc3s700anfgg484-4
|
| 14 |
|
|
# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
|
| 15 |
|
|
# set_property edif_top_file "C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/ise/sport_top/sport_top.ngc" [ get_property srcset [ current_run ] ]
|
| 16 |
|
|
# add_files -norecurse { {C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/ise/sport_top} }
|
| 17 |
|
|
# set_param project.pinAheadLayout yes
|
| 18 |
|
|
# set_property target_constrs_file "sport_top.ucf" [current_fileset -constrset]
|
| 19 |
|
|
Adding file 'C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/ise/sport_top/sport_top.ucf' to fileset 'constrs_1'
|
| 20 |
|
|
# add_files [list {sport_top.ucf}] -fileset [get_property constrset [current_run]]
|
| 21 |
|
|
# link_design
|
| 22 |
|
|
Design is defaulting to srcset: sources_1
|
| 23 |
|
|
Design is defaulting to constrset: constrs_1
|
| 24 |
|
|
Design is defaulting to project part: xc3s700anfgg484-4
|
| 25 |
|
|
Release 14.7 - ngc2edif P.20131013 (nt64)
|
| 26 |
|
|
|
| 27 |
|
|
Reading design sport_top.ngc ...
|
| 28 |
|
|
|
| 29 |
|
|
Processing design ...
|
| 30 |
|
|
|
| 31 |
|
|
Preping design's macros ...
|
| 32 |
|
|
|
| 33 |
|
|
sport_top is not reconstructed, because there are some missing bus signals.
|
| 34 |
|
|
|
| 35 |
|
|
sport_top is not reconstructed, because there are some missing bus signals.
|
| 36 |
|
|
|
| 37 |
|
|
Writing EDIF netlist file sport_top.edif ...
|
| 38 |
|
|
|
| 39 |
|
|
|
| 40 |
|
|
|
| 41 |
|
|
Finished Parsing EDIF File [./planAhead_run_2/sport_top.data/cache/sport_top_ngc_zx.edif]
|
| 42 |
|
|
|
| 43 |
|
|
Parsing EDIF File [C:/Xilinx/14.7/ISE_DS/PlanAhead/data\./parts/xilinx/spartan3a/hd_int_macros.edn]
|
| 44 |
|
|
|
| 45 |
|
|
Loading clock regions from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan3a/spartan3a/xc3s700an/ClockRegion.xml
|
| 46 |
|
|
|
| 47 |
|
|
Loading package from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan3a/spartan3a/xc3s700an/fgg484/Package.xml
|
| 48 |
|
|
|
| 49 |
|
|
INFO: [Device 21-19] Loading pkg sso from C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan3a/spartan3a/xc3s700an/fgg484/SSORules.xml
|
| 50 |
|
|
|
| 51 |
|
|
INFO: [Timing 38-77] Reading timing library C:/Xilinx/14.7/ISE_DS/PlanAhead/data\parts/xilinx/spartan3a/spartan3a/spartan3a-4.lib.
|
| 52 |
|
|
|
| 53 |
|
|
|
| 54 |
|
|
|
| 55 |
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
| 56 |
|
|
No Unisim elements were transformed.
|
| 57 |
|
|
|
| 58 |
|
|
Phase 0 | Netlist Checksum: 0b0d73e8
|
| 59 |
|
|
link_design: Time (s): elapsed = 00:00:15 . Memory (MB): peak = 561.336 ; gain = 138.750
|
| 60 |
|
|
startgroup
|
| 61 |
|
|
set_property package_pin A2 [get_ports DRxPRI]
|
| 62 |
|
|
endgroup
|
| 63 |
|
|
startgroup
|
| 64 |
|
|
set_property package_pin A3 [get_ports DRxSEC]
|
| 65 |
|
|
endgroup
|
| 66 |
|
|
startgroup
|
| 67 |
|
|
set_property package_pin A4 [get_ports DTxPRI]
|
| 68 |
|
|
endgroup
|
| 69 |
|
|
set_property package_pin "" [get_ports [list DTxSEC]]
|
| 70 |
|
|
set_property package_pin "" [get_ports [list RSCLKx]]
|
| 71 |
|
|
startgroup
|
| 72 |
|
|
|
| 73 |
|
|
endgroup
|
| 74 |
|
|
startgroup
|
| 75 |
|
|
set_property package_pin A6 [get_ports RSCLKx]
|
| 76 |
|
|
endgroup
|
| 77 |
|
|
set_property package_pin "" [get_ports [list rx_int]]
|
| 78 |
|
|
save_constraints
|
| 79 |
|
|
exit
|
| 80 |
|
|
ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
|
| 81 |
|
|
INFO: [Common 17-206] Exiting PlanAhead at Fri Feb 20 14:04:22 2015...
|
| 82 |
|
|
INFO: [Common 17-83] Releasing license: PlanAhead
|
| 83 |
|
|
|
