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jeaander |
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Release 14.7 Trace (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 4
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-n 3 -fastpaths -xml sport_top.twx sport_top.ncd -o sport_top.twr sport_top.pcf
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-ucf sport_top.ucf
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Design file: sport_top.ncd
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Physical constraint file: sport_top.pcf
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Device,package,speed: xc3s700an,fgg484,-4 (PRODUCTION 1.42 2013-10-13)
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Report level: verbose report
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Environment Variable Effect
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-------------------- ------
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NONE No environment variables were set
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--------------------------------------------------------------------------------
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INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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option. All paths that are not constrained will be reported in the
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unconstrained paths section(s) of the report.
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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a 50 Ohm transmission line loading model. For the details of this model,
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and for more information on accounting for different loading conditions,
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please see the device datasheet.
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INFO:Timing:3390 - This architecture does not support a default System Jitter
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value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
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Uncertainty calculation.
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INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
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'Phase Error' calculations, these terms will be zero in the Clock
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Uncertainty calculation. Please make appropriate modification to
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SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
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Error.
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================================================================================
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Timing constraint: TS_rxclk = PERIOD TIMEGRP "rxclk" 20 ns HIGH 50%;
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For more information, see Period Analysis in the Timing Closure User Guide (UG612).
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Minimum period is 1.602ns.
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--------------------------------------------------------------------------------
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Component Switching Limit Checks: TS_rxclk = PERIOD TIMEGRP "rxclk" 20 ns HIGH 50%;
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--------------------------------------------------------------------------------
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Slack: 18.398ns (period - (min low pulse limit / (low pulse / period)))
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Period: 20.000ns
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Low pulse: 10.000ns
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Low pulse limit: 0.801ns (Tcl)
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Physical resource: rxfs_rnm0/CLK
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Logical resource: rxfs_rnm0/CK
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Location pin: SLICE_X6Y54.CLK
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Clock network: RSCLKx_OBUF
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--------------------------------------------------------------------------------
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Slack: 18.398ns (period - (min high pulse limit / (high pulse / period)))
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Period: 20.000ns
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High pulse: 10.000ns
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High pulse limit: 0.801ns (Tch)
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Physical resource: rxfs_rnm0/CLK
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Logical resource: rxfs_rnm0/CK
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Location pin: SLICE_X6Y54.CLK
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Clock network: RSCLKx_OBUF
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--------------------------------------------------------------------------------
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Slack: 18.398ns (period - min period limit)
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Period: 20.000ns
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Min period limit: 1.602ns (624.220MHz) (Tcp)
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Physical resource: rxfs_rnm0/CLK
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Logical resource: rxfs_rnm0/CK
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Location pin: SLICE_X6Y54.CLK
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Clock network: RSCLKx_OBUF
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--------------------------------------------------------------------------------
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================================================================================
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Timing constraint: TS_txclk = PERIOD TIMEGRP "txclk" 20 ns HIGH 50%;
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For more information, see Period Analysis in the Timing Closure User Guide (UG612).
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128 paths analyzed, 60 endpoints analyzed, 0 failing endpoints
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Minimum period is 4.635ns.
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--------------------------------------------------------------------------------
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Paths for end point state_FSM_FFd2 (SLICE_X4Y53.F2), 10 paths
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--------------------------------------------------------------------------------
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Slack (setup path): 15.365ns (requirement - (data path - clock path skew + uncertainty))
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Source: txpacketCnt_tx_7 (FF)
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Destination: state_FSM_FFd2 (FF)
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Requirement: 20.000ns
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Data Path Delay: 4.672ns (Levels of Logic = 3)
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Clock Path Skew: 0.037ns (0.056 - 0.019)
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Source Clock: TSCLKx_OBUF rising at 0.000ns
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Destination Clock: TSCLKx_OBUF rising at 20.000ns
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Clock Uncertainty: 0.000ns
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Maximum Data Path: txpacketCnt_tx_7 to state_FSM_FFd2
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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SLICE_X4Y60.XQ Tcko 0.631 txpacketCnt_tx<7>
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txpacketCnt_tx_7
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SLICE_X5Y51.G3 net (fanout=2) 1.234 txpacketCnt_tx<7>
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SLICE_X5Y51.COUT Topcyg 1.178 Mcompar_state_cmp_eq0001_cy<3>
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Mcompar_state_cmp_eq0001_lut<3>
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Mcompar_state_cmp_eq0001_cy<3>
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SLICE_X5Y52.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<3>
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SLICE_X5Y52.XB Tcinxb 0.296 Mcompar_state_cmp_eq0001_cy<4>
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Mcompar_state_cmp_eq0001_cy<4>
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SLICE_X4Y53.F2 net (fanout=1) 0.531 Mcompar_state_cmp_eq0001_cy<4>
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SLICE_X4Y53.CLK Tfck 0.802 state_FSM_FFd2
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state_FSM_FFd2-In11
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state_FSM_FFd2
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------------------------------------------------- ---------------------------
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Total 4.672ns (2.907ns logic, 1.765ns route)
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(62.2% logic, 37.8% route)
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--------------------------------------------------------------------------------
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Slack (setup path): 15.387ns (requirement - (data path - clock path skew + uncertainty))
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Source: txpacketCnt_tx_3 (FF)
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Destination: state_FSM_FFd2 (FF)
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Requirement: 20.000ns
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Data Path Delay: 4.634ns (Levels of Logic = 4)
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Clock Path Skew: 0.021ns (0.056 - 0.035)
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Source Clock: TSCLKx_OBUF rising at 0.000ns
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Destination Clock: TSCLKx_OBUF rising at 20.000ns
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Clock Uncertainty: 0.000ns
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Maximum Data Path: txpacketCnt_tx_3 to state_FSM_FFd2
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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SLICE_X4Y58.XQ Tcko 0.631 txpacketCnt_tx<3>
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txpacketCnt_tx_3
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SLICE_X5Y50.G2 net (fanout=2) 1.066 txpacketCnt_tx<3>
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SLICE_X5Y50.COUT Topcyg 1.178 Mcompar_state_cmp_eq0001_cy<1>
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Mcompar_state_cmp_eq0001_lut<1>
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Mcompar_state_cmp_eq0001_cy<1>
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SLICE_X5Y51.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<1>
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SLICE_X5Y51.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<3>
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Mcompar_state_cmp_eq0001_cy<2>
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Mcompar_state_cmp_eq0001_cy<3>
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SLICE_X5Y52.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<3>
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SLICE_X5Y52.XB Tcinxb 0.296 Mcompar_state_cmp_eq0001_cy<4>
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Mcompar_state_cmp_eq0001_cy<4>
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SLICE_X4Y53.F2 net (fanout=1) 0.531 Mcompar_state_cmp_eq0001_cy<4>
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SLICE_X4Y53.CLK Tfck 0.802 state_FSM_FFd2
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state_FSM_FFd2-In11
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state_FSM_FFd2
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------------------------------------------------- ---------------------------
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Total 4.634ns (3.037ns logic, 1.597ns route)
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(65.5% logic, 34.5% route)
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--------------------------------------------------------------------------------
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Slack (setup path): 15.400ns (requirement - (data path - clock path skew + uncertainty))
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Source: txpacketCnt_tx_4 (FF)
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Destination: state_FSM_FFd2 (FF)
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Requirement: 20.000ns
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Data Path Delay: 4.637ns (Levels of Logic = 3)
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Clock Path Skew: 0.037ns (0.056 - 0.019)
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Source Clock: TSCLKx_OBUF rising at 0.000ns
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Destination Clock: TSCLKx_OBUF rising at 20.000ns
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Clock Uncertainty: 0.000ns
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Maximum Data Path: txpacketCnt_tx_4 to state_FSM_FFd2
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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SLICE_X4Y61.YQ Tcko 0.676 txpacketCnt_tx<5>
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txpacketCnt_tx_4
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SLICE_X5Y51.F3 net (fanout=2) 1.137 txpacketCnt_tx<4>
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SLICE_X5Y51.COUT Topcyf 1.195 Mcompar_state_cmp_eq0001_cy<3>
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Mcompar_state_cmp_eq0001_lut<2>
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Mcompar_state_cmp_eq0001_cy<2>
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Mcompar_state_cmp_eq0001_cy<3>
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SLICE_X5Y52.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<3>
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SLICE_X5Y52.XB Tcinxb 0.296 Mcompar_state_cmp_eq0001_cy<4>
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Mcompar_state_cmp_eq0001_cy<4>
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SLICE_X4Y53.F2 net (fanout=1) 0.531 Mcompar_state_cmp_eq0001_cy<4>
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SLICE_X4Y53.CLK Tfck 0.802 state_FSM_FFd2
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state_FSM_FFd2-In11
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state_FSM_FFd2
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------------------------------------------------- ---------------------------
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Total 4.637ns (2.969ns logic, 1.668ns route)
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(64.0% logic, 36.0% route)
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--------------------------------------------------------------------------------
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Paths for end point state_FSM_FFd2 (SLICE_X4Y53.F3), 5 paths
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--------------------------------------------------------------------------------
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Slack (setup path): 15.427ns (requirement - (data path - clock path skew + uncertainty))
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Source: txsampleCnt_tx_4 (FF)
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Destination: state_FSM_FFd2 (FF)
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Requirement: 20.000ns
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Data Path Delay: 4.569ns (Levels of Logic = 4)
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Clock Path Skew: -0.004ns (0.056 - 0.060)
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Source Clock: TSCLKx_OBUF rising at 0.000ns
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Destination Clock: TSCLKx_OBUF rising at 20.000ns
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Clock Uncertainty: 0.000ns
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Maximum Data Path: txsampleCnt_tx_4 to state_FSM_FFd2
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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SLICE_X4Y55.XQ Tcko 0.631 txsampleCnt_tx<4>
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txsampleCnt_tx_4
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SLICE_X5Y53.G2 net (fanout=2) 0.903 txsampleCnt_tx<4>
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SLICE_X5Y53.Y Tilo 0.648 state_FSM_FFd1-In_bdd2
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state_FSM_FFd1-In51
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SLICE_X5Y53.F4 net (fanout=1) 0.044 state_FSM_FFd1-In51/O
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SLICE_X5Y53.X Tilo 0.643 state_FSM_FFd1-In_bdd2
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state_FSM_FFd1-In31
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SLICE_X4Y53.G4 net (fanout=2) 0.148 state_FSM_FFd1-In_bdd2
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SLICE_X4Y53.Y Tilo 0.707 state_FSM_FFd2
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state_FSM_FFd1-In21_SW0
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SLICE_X4Y53.F3 net (fanout=1) 0.043 state_FSM_FFd1-In21_SW0/O
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SLICE_X4Y53.CLK Tfck 0.802 state_FSM_FFd2
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state_FSM_FFd2-In11
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state_FSM_FFd2
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------------------------------------------------- ---------------------------
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Total 4.569ns (3.431ns logic, 1.138ns route)
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(75.1% logic, 24.9% route)
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--------------------------------------------------------------------------------
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Slack (setup path): 15.471ns (requirement - (data path - clock path skew + uncertainty))
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Source: txsampleCnt_tx_1 (FF)
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| 225 |
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Destination: state_FSM_FFd2 (FF)
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| 226 |
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Requirement: 20.000ns
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| 227 |
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Data Path Delay: 4.525ns (Levels of Logic = 4)
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| 228 |
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Clock Path Skew: -0.004ns (0.056 - 0.060)
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| 229 |
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Source Clock: TSCLKx_OBUF rising at 0.000ns
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| 230 |
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Destination Clock: TSCLKx_OBUF rising at 20.000ns
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| 231 |
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Clock Uncertainty: 0.000ns
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| 232 |
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| 233 |
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Maximum Data Path: txsampleCnt_tx_1 to state_FSM_FFd2
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| 234 |
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Location Delay type Delay(ns) Physical Resource
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| 235 |
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Logical Resource(s)
|
| 236 |
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------------------------------------------------- -------------------
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| 237 |
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SLICE_X5Y54.XQ Tcko 0.591 txsampleCnt_tx<1>
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| 238 |
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txsampleCnt_tx_1
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| 239 |
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SLICE_X4Y54.F1 net (fanout=4) 0.579 txsampleCnt_tx<1>
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| 240 |
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SLICE_X4Y54.X Tilo 0.692 txsampleCnt_tx<2>
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| 241 |
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state_FSM_FFd1-In41_SW0
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| 242 |
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SLICE_X5Y53.F3 net (fanout=1) 0.320 N21
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| 243 |
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SLICE_X5Y53.X Tilo 0.643 state_FSM_FFd1-In_bdd2
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| 244 |
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state_FSM_FFd1-In31
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| 245 |
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SLICE_X4Y53.G4 net (fanout=2) 0.148 state_FSM_FFd1-In_bdd2
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| 246 |
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SLICE_X4Y53.Y Tilo 0.707 state_FSM_FFd2
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| 247 |
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state_FSM_FFd1-In21_SW0
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| 248 |
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SLICE_X4Y53.F3 net (fanout=1) 0.043 state_FSM_FFd1-In21_SW0/O
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| 249 |
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SLICE_X4Y53.CLK Tfck 0.802 state_FSM_FFd2
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| 250 |
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state_FSM_FFd2-In11
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| 251 |
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state_FSM_FFd2
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| 252 |
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------------------------------------------------- ---------------------------
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| 253 |
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Total 4.525ns (3.435ns logic, 1.090ns route)
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| 254 |
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(75.9% logic, 24.1% route)
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| 255 |
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| 256 |
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--------------------------------------------------------------------------------
|
| 257 |
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Slack (setup path): 15.651ns (requirement - (data path - clock path skew + uncertainty))
|
| 258 |
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Source: txsampleCnt_tx_3 (FF)
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| 259 |
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Destination: state_FSM_FFd2 (FF)
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| 260 |
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Requirement: 20.000ns
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| 261 |
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Data Path Delay: 4.345ns (Levels of Logic = 4)
|
| 262 |
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Clock Path Skew: -0.004ns (0.056 - 0.060)
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| 263 |
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Source Clock: TSCLKx_OBUF rising at 0.000ns
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| 264 |
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Destination Clock: TSCLKx_OBUF rising at 20.000ns
|
| 265 |
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Clock Uncertainty: 0.000ns
|
| 266 |
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|
| 267 |
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Maximum Data Path: txsampleCnt_tx_3 to state_FSM_FFd2
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| 268 |
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Location Delay type Delay(ns) Physical Resource
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| 269 |
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Logical Resource(s)
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| 270 |
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------------------------------------------------- -------------------
|
| 271 |
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SLICE_X5Y55.XQ Tcko 0.591 txsampleCnt_tx<3>
|
| 272 |
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txsampleCnt_tx_3
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| 273 |
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SLICE_X5Y53.G4 net (fanout=3) 0.719 txsampleCnt_tx<3>
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| 274 |
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SLICE_X5Y53.Y Tilo 0.648 state_FSM_FFd1-In_bdd2
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| 275 |
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state_FSM_FFd1-In51
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| 276 |
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SLICE_X5Y53.F4 net (fanout=1) 0.044 state_FSM_FFd1-In51/O
|
| 277 |
|
|
SLICE_X5Y53.X Tilo 0.643 state_FSM_FFd1-In_bdd2
|
| 278 |
|
|
state_FSM_FFd1-In31
|
| 279 |
|
|
SLICE_X4Y53.G4 net (fanout=2) 0.148 state_FSM_FFd1-In_bdd2
|
| 280 |
|
|
SLICE_X4Y53.Y Tilo 0.707 state_FSM_FFd2
|
| 281 |
|
|
state_FSM_FFd1-In21_SW0
|
| 282 |
|
|
SLICE_X4Y53.F3 net (fanout=1) 0.043 state_FSM_FFd1-In21_SW0/O
|
| 283 |
|
|
SLICE_X4Y53.CLK Tfck 0.802 state_FSM_FFd2
|
| 284 |
|
|
state_FSM_FFd2-In11
|
| 285 |
|
|
state_FSM_FFd2
|
| 286 |
|
|
------------------------------------------------- ---------------------------
|
| 287 |
|
|
Total 4.345ns (3.391ns logic, 0.954ns route)
|
| 288 |
|
|
(78.0% logic, 22.0% route)
|
| 289 |
|
|
|
| 290 |
|
|
--------------------------------------------------------------------------------
|
| 291 |
|
|
|
| 292 |
|
|
Paths for end point txpacketCnt_tx_9 (SLICE_X4Y62.F2), 10 paths
|
| 293 |
|
|
--------------------------------------------------------------------------------
|
| 294 |
|
|
Slack (setup path): 15.504ns (requirement - (data path - clock path skew + uncertainty))
|
| 295 |
|
|
Source: txpacketCnt_tx_1 (FF)
|
| 296 |
|
|
Destination: txpacketCnt_tx_9 (FF)
|
| 297 |
|
|
Requirement: 20.000ns
|
| 298 |
|
|
Data Path Delay: 4.467ns (Levels of Logic = 6)
|
| 299 |
|
|
Clock Path Skew: -0.029ns (0.006 - 0.035)
|
| 300 |
|
|
Source Clock: TSCLKx_OBUF rising at 0.000ns
|
| 301 |
|
|
Destination Clock: TSCLKx_OBUF rising at 20.000ns
|
| 302 |
|
|
Clock Uncertainty: 0.000ns
|
| 303 |
|
|
|
| 304 |
|
|
Maximum Data Path: txpacketCnt_tx_1 to txpacketCnt_tx_9
|
| 305 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 306 |
|
|
Logical Resource(s)
|
| 307 |
|
|
------------------------------------------------- -------------------
|
| 308 |
|
|
SLICE_X4Y59.XQ Tcko 0.631 txpacketCnt_tx<1>
|
| 309 |
|
|
txpacketCnt_tx_1
|
| 310 |
|
|
SLICE_X5Y58.G1 net (fanout=2) 0.528 txpacketCnt_tx<1>
|
| 311 |
|
|
SLICE_X5Y58.COUT Topcyg 1.178 txpacketCnt_tx_addsub0000<0>
|
| 312 |
|
|
txpacketCnt_tx<1>_rt
|
| 313 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<1>
|
| 314 |
|
|
SLICE_X5Y59.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<1>
|
| 315 |
|
|
SLICE_X5Y59.COUT Tbyp 0.130 txpacketCnt_tx_addsub0000<2>
|
| 316 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<2>
|
| 317 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<3>
|
| 318 |
|
|
SLICE_X5Y60.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<3>
|
| 319 |
|
|
SLICE_X5Y60.COUT Tbyp 0.130 txpacketCnt_tx_addsub0000<4>
|
| 320 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<4>
|
| 321 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<5>
|
| 322 |
|
|
SLICE_X5Y61.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<5>
|
| 323 |
|
|
SLICE_X5Y61.COUT Tbyp 0.130 txpacketCnt_tx_addsub0000<6>
|
| 324 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<6>
|
| 325 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<7>
|
| 326 |
|
|
SLICE_X5Y62.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<7>
|
| 327 |
|
|
SLICE_X5Y62.Y Tciny 0.864 txpacketCnt_tx_addsub0000<8>
|
| 328 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<8>
|
| 329 |
|
|
Madd_txpacketCnt_tx_addsub0000_xor<9>
|
| 330 |
|
|
SLICE_X4Y62.F2 net (fanout=1) 0.074 txpacketCnt_tx_addsub0000<9>
|
| 331 |
|
|
SLICE_X4Y62.CLK Tfck 0.802 txpacketCnt_tx<9>
|
| 332 |
|
|
txpacketCnt_tx_mux0000<9>1
|
| 333 |
|
|
txpacketCnt_tx_9
|
| 334 |
|
|
------------------------------------------------- ---------------------------
|
| 335 |
|
|
Total 4.467ns (3.865ns logic, 0.602ns route)
|
| 336 |
|
|
(86.5% logic, 13.5% route)
|
| 337 |
|
|
|
| 338 |
|
|
--------------------------------------------------------------------------------
|
| 339 |
|
|
Slack (setup path): 15.560ns (requirement - (data path - clock path skew + uncertainty))
|
| 340 |
|
|
Source: txpacketCnt_tx_0 (FF)
|
| 341 |
|
|
Destination: txpacketCnt_tx_9 (FF)
|
| 342 |
|
|
Requirement: 20.000ns
|
| 343 |
|
|
Data Path Delay: 4.411ns (Levels of Logic = 6)
|
| 344 |
|
|
Clock Path Skew: -0.029ns (0.006 - 0.035)
|
| 345 |
|
|
Source Clock: TSCLKx_OBUF rising at 0.000ns
|
| 346 |
|
|
Destination Clock: TSCLKx_OBUF rising at 20.000ns
|
| 347 |
|
|
Clock Uncertainty: 0.000ns
|
| 348 |
|
|
|
| 349 |
|
|
Maximum Data Path: txpacketCnt_tx_0 to txpacketCnt_tx_9
|
| 350 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 351 |
|
|
Logical Resource(s)
|
| 352 |
|
|
------------------------------------------------- -------------------
|
| 353 |
|
|
SLICE_X4Y59.YQ Tcko 0.676 txpacketCnt_tx<1>
|
| 354 |
|
|
txpacketCnt_tx_0
|
| 355 |
|
|
SLICE_X5Y58.F4 net (fanout=2) 0.410 txpacketCnt_tx<0>
|
| 356 |
|
|
SLICE_X5Y58.COUT Topcyf 1.195 txpacketCnt_tx_addsub0000<0>
|
| 357 |
|
|
Madd_txpacketCnt_tx_addsub0000_lut<0>_INV_0
|
| 358 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<0>
|
| 359 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<1>
|
| 360 |
|
|
SLICE_X5Y59.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<1>
|
| 361 |
|
|
SLICE_X5Y59.COUT Tbyp 0.130 txpacketCnt_tx_addsub0000<2>
|
| 362 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<2>
|
| 363 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<3>
|
| 364 |
|
|
SLICE_X5Y60.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<3>
|
| 365 |
|
|
SLICE_X5Y60.COUT Tbyp 0.130 txpacketCnt_tx_addsub0000<4>
|
| 366 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<4>
|
| 367 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<5>
|
| 368 |
|
|
SLICE_X5Y61.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<5>
|
| 369 |
|
|
SLICE_X5Y61.COUT Tbyp 0.130 txpacketCnt_tx_addsub0000<6>
|
| 370 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<6>
|
| 371 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<7>
|
| 372 |
|
|
SLICE_X5Y62.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<7>
|
| 373 |
|
|
SLICE_X5Y62.Y Tciny 0.864 txpacketCnt_tx_addsub0000<8>
|
| 374 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<8>
|
| 375 |
|
|
Madd_txpacketCnt_tx_addsub0000_xor<9>
|
| 376 |
|
|
SLICE_X4Y62.F2 net (fanout=1) 0.074 txpacketCnt_tx_addsub0000<9>
|
| 377 |
|
|
SLICE_X4Y62.CLK Tfck 0.802 txpacketCnt_tx<9>
|
| 378 |
|
|
txpacketCnt_tx_mux0000<9>1
|
| 379 |
|
|
txpacketCnt_tx_9
|
| 380 |
|
|
------------------------------------------------- ---------------------------
|
| 381 |
|
|
Total 4.411ns (3.927ns logic, 0.484ns route)
|
| 382 |
|
|
(89.0% logic, 11.0% route)
|
| 383 |
|
|
|
| 384 |
|
|
--------------------------------------------------------------------------------
|
| 385 |
|
|
Slack (setup path): 15.564ns (requirement - (data path - clock path skew + uncertainty))
|
| 386 |
|
|
Source: txpacketCnt_tx_2 (FF)
|
| 387 |
|
|
Destination: txpacketCnt_tx_9 (FF)
|
| 388 |
|
|
Requirement: 20.000ns
|
| 389 |
|
|
Data Path Delay: 4.407ns (Levels of Logic = 5)
|
| 390 |
|
|
Clock Path Skew: -0.029ns (0.006 - 0.035)
|
| 391 |
|
|
Source Clock: TSCLKx_OBUF rising at 0.000ns
|
| 392 |
|
|
Destination Clock: TSCLKx_OBUF rising at 20.000ns
|
| 393 |
|
|
Clock Uncertainty: 0.000ns
|
| 394 |
|
|
|
| 395 |
|
|
Maximum Data Path: txpacketCnt_tx_2 to txpacketCnt_tx_9
|
| 396 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 397 |
|
|
Logical Resource(s)
|
| 398 |
|
|
------------------------------------------------- -------------------
|
| 399 |
|
|
SLICE_X4Y58.YQ Tcko 0.676 txpacketCnt_tx<3>
|
| 400 |
|
|
txpacketCnt_tx_2
|
| 401 |
|
|
SLICE_X5Y59.F3 net (fanout=2) 0.536 txpacketCnt_tx<2>
|
| 402 |
|
|
SLICE_X5Y59.COUT Topcyf 1.195 txpacketCnt_tx_addsub0000<2>
|
| 403 |
|
|
txpacketCnt_tx<2>_rt
|
| 404 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<2>
|
| 405 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<3>
|
| 406 |
|
|
SLICE_X5Y60.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<3>
|
| 407 |
|
|
SLICE_X5Y60.COUT Tbyp 0.130 txpacketCnt_tx_addsub0000<4>
|
| 408 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<4>
|
| 409 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<5>
|
| 410 |
|
|
SLICE_X5Y61.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<5>
|
| 411 |
|
|
SLICE_X5Y61.COUT Tbyp 0.130 txpacketCnt_tx_addsub0000<6>
|
| 412 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<6>
|
| 413 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<7>
|
| 414 |
|
|
SLICE_X5Y62.CIN net (fanout=1) 0.000 Madd_txpacketCnt_tx_addsub0000_cy<7>
|
| 415 |
|
|
SLICE_X5Y62.Y Tciny 0.864 txpacketCnt_tx_addsub0000<8>
|
| 416 |
|
|
Madd_txpacketCnt_tx_addsub0000_cy<8>
|
| 417 |
|
|
Madd_txpacketCnt_tx_addsub0000_xor<9>
|
| 418 |
|
|
SLICE_X4Y62.F2 net (fanout=1) 0.074 txpacketCnt_tx_addsub0000<9>
|
| 419 |
|
|
SLICE_X4Y62.CLK Tfck 0.802 txpacketCnt_tx<9>
|
| 420 |
|
|
txpacketCnt_tx_mux0000<9>1
|
| 421 |
|
|
txpacketCnt_tx_9
|
| 422 |
|
|
------------------------------------------------- ---------------------------
|
| 423 |
|
|
Total 4.407ns (3.797ns logic, 0.610ns route)
|
| 424 |
|
|
(86.2% logic, 13.8% route)
|
| 425 |
|
|
|
| 426 |
|
|
--------------------------------------------------------------------------------
|
| 427 |
|
|
|
| 428 |
|
|
Hold Paths: TS_txclk = PERIOD TIMEGRP "txclk" 20 ns HIGH 50%;
|
| 429 |
|
|
--------------------------------------------------------------------------------
|
| 430 |
|
|
|
| 431 |
|
|
Paths for end point txsampleCnt_tx_1 (SLICE_X5Y54.F4), 1 path
|
| 432 |
|
|
--------------------------------------------------------------------------------
|
| 433 |
|
|
Slack (hold path): 1.314ns (requirement - (clock path skew + uncertainty - data path))
|
| 434 |
|
|
Source: txsampleCnt_tx_1 (FF)
|
| 435 |
|
|
Destination: txsampleCnt_tx_1 (FF)
|
| 436 |
|
|
Requirement: 0.000ns
|
| 437 |
|
|
Data Path Delay: 1.314ns (Levels of Logic = 1)
|
| 438 |
|
|
Clock Path Skew: 0.000ns
|
| 439 |
|
|
Source Clock: TSCLKx_OBUF rising at 20.000ns
|
| 440 |
|
|
Destination Clock: TSCLKx_OBUF rising at 20.000ns
|
| 441 |
|
|
Clock Uncertainty: 0.000ns
|
| 442 |
|
|
|
| 443 |
|
|
Minimum Data Path: txsampleCnt_tx_1 to txsampleCnt_tx_1
|
| 444 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 445 |
|
|
Logical Resource(s)
|
| 446 |
|
|
------------------------------------------------- -------------------
|
| 447 |
|
|
SLICE_X5Y54.XQ Tcko 0.473 txsampleCnt_tx<1>
|
| 448 |
|
|
txsampleCnt_tx_1
|
| 449 |
|
|
SLICE_X5Y54.F4 net (fanout=4) 0.375 txsampleCnt_tx<1>
|
| 450 |
|
|
SLICE_X5Y54.CLK Tckf (-Th) -0.466 txsampleCnt_tx<1>
|
| 451 |
|
|
txsampleCnt_tx_mux0000<1>1
|
| 452 |
|
|
txsampleCnt_tx_1
|
| 453 |
|
|
------------------------------------------------- ---------------------------
|
| 454 |
|
|
Total 1.314ns (0.939ns logic, 0.375ns route)
|
| 455 |
|
|
(71.5% logic, 28.5% route)
|
| 456 |
|
|
|
| 457 |
|
|
--------------------------------------------------------------------------------
|
| 458 |
|
|
|
| 459 |
|
|
Paths for end point txsampleCnt_tx_0 (SLICE_X5Y54.G4), 1 path
|
| 460 |
|
|
--------------------------------------------------------------------------------
|
| 461 |
|
|
Slack (hold path): 1.363ns (requirement - (clock path skew + uncertainty - data path))
|
| 462 |
|
|
Source: state_FSM_FFd2 (FF)
|
| 463 |
|
|
Destination: txsampleCnt_tx_0 (FF)
|
| 464 |
|
|
Requirement: 0.000ns
|
| 465 |
|
|
Data Path Delay: 1.367ns (Levels of Logic = 1)
|
| 466 |
|
|
Clock Path Skew: 0.004ns (0.060 - 0.056)
|
| 467 |
|
|
Source Clock: TSCLKx_OBUF rising at 20.000ns
|
| 468 |
|
|
Destination Clock: TSCLKx_OBUF rising at 20.000ns
|
| 469 |
|
|
Clock Uncertainty: 0.000ns
|
| 470 |
|
|
|
| 471 |
|
|
Minimum Data Path: state_FSM_FFd2 to txsampleCnt_tx_0
|
| 472 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 473 |
|
|
Logical Resource(s)
|
| 474 |
|
|
------------------------------------------------- -------------------
|
| 475 |
|
|
SLICE_X4Y53.XQ Tcko 0.505 state_FSM_FFd2
|
| 476 |
|
|
state_FSM_FFd2
|
| 477 |
|
|
SLICE_X5Y54.G4 net (fanout=18) 0.392 state_FSM_FFd2
|
| 478 |
|
|
SLICE_X5Y54.CLK Tckg (-Th) -0.470 txsampleCnt_tx<1>
|
| 479 |
|
|
txsampleCnt_tx_mux0000<0>1
|
| 480 |
|
|
txsampleCnt_tx_0
|
| 481 |
|
|
------------------------------------------------- ---------------------------
|
| 482 |
|
|
Total 1.367ns (0.975ns logic, 0.392ns route)
|
| 483 |
|
|
(71.3% logic, 28.7% route)
|
| 484 |
|
|
|
| 485 |
|
|
--------------------------------------------------------------------------------
|
| 486 |
|
|
|
| 487 |
|
|
Paths for end point txsampleCnt_tx_3 (SLICE_X5Y55.F3), 1 path
|
| 488 |
|
|
--------------------------------------------------------------------------------
|
| 489 |
|
|
Slack (hold path): 1.418ns (requirement - (clock path skew + uncertainty - data path))
|
| 490 |
|
|
Source: state_FSM_FFd2 (FF)
|
| 491 |
|
|
Destination: txsampleCnt_tx_3 (FF)
|
| 492 |
|
|
Requirement: 0.000ns
|
| 493 |
|
|
Data Path Delay: 1.422ns (Levels of Logic = 1)
|
| 494 |
|
|
Clock Path Skew: 0.004ns (0.060 - 0.056)
|
| 495 |
|
|
Source Clock: TSCLKx_OBUF rising at 20.000ns
|
| 496 |
|
|
Destination Clock: TSCLKx_OBUF rising at 20.000ns
|
| 497 |
|
|
Clock Uncertainty: 0.000ns
|
| 498 |
|
|
|
| 499 |
|
|
Minimum Data Path: state_FSM_FFd2 to txsampleCnt_tx_3
|
| 500 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 501 |
|
|
Logical Resource(s)
|
| 502 |
|
|
------------------------------------------------- -------------------
|
| 503 |
|
|
SLICE_X4Y53.XQ Tcko 0.505 state_FSM_FFd2
|
| 504 |
|
|
state_FSM_FFd2
|
| 505 |
|
|
SLICE_X5Y55.F3 net (fanout=18) 0.451 state_FSM_FFd2
|
| 506 |
|
|
SLICE_X5Y55.CLK Tckf (-Th) -0.466 txsampleCnt_tx<3>
|
| 507 |
|
|
txsampleCnt_tx_mux0000<3>1
|
| 508 |
|
|
txsampleCnt_tx_3
|
| 509 |
|
|
------------------------------------------------- ---------------------------
|
| 510 |
|
|
Total 1.422ns (0.971ns logic, 0.451ns route)
|
| 511 |
|
|
(68.3% logic, 31.7% route)
|
| 512 |
|
|
|
| 513 |
|
|
--------------------------------------------------------------------------------
|
| 514 |
|
|
|
| 515 |
|
|
Component Switching Limit Checks: TS_txclk = PERIOD TIMEGRP "txclk" 20 ns HIGH 50%;
|
| 516 |
|
|
--------------------------------------------------------------------------------
|
| 517 |
|
|
Slack: 18.398ns (period - (min low pulse limit / (low pulse / period)))
|
| 518 |
|
|
Period: 20.000ns
|
| 519 |
|
|
Low pulse: 10.000ns
|
| 520 |
|
|
Low pulse limit: 0.801ns (Tcl)
|
| 521 |
|
|
Physical resource: state_FSM_FFd1/CLK
|
| 522 |
|
|
Logical resource: state_FSM_FFd1/CK
|
| 523 |
|
|
Location pin: SLICE_X4Y52.CLK
|
| 524 |
|
|
Clock network: TSCLKx_OBUF
|
| 525 |
|
|
--------------------------------------------------------------------------------
|
| 526 |
|
|
Slack: 18.398ns (period - (min high pulse limit / (high pulse / period)))
|
| 527 |
|
|
Period: 20.000ns
|
| 528 |
|
|
High pulse: 10.000ns
|
| 529 |
|
|
High pulse limit: 0.801ns (Tch)
|
| 530 |
|
|
Physical resource: state_FSM_FFd1/CLK
|
| 531 |
|
|
Logical resource: state_FSM_FFd1/CK
|
| 532 |
|
|
Location pin: SLICE_X4Y52.CLK
|
| 533 |
|
|
Clock network: TSCLKx_OBUF
|
| 534 |
|
|
--------------------------------------------------------------------------------
|
| 535 |
|
|
Slack: 18.398ns (period - min period limit)
|
| 536 |
|
|
Period: 20.000ns
|
| 537 |
|
|
Min period limit: 1.602ns (624.220MHz) (Tcp)
|
| 538 |
|
|
Physical resource: state_FSM_FFd1/CLK
|
| 539 |
|
|
Logical resource: state_FSM_FFd1/CK
|
| 540 |
|
|
Location pin: SLICE_X4Y52.CLK
|
| 541 |
|
|
Clock network: TSCLKx_OBUF
|
| 542 |
|
|
--------------------------------------------------------------------------------
|
| 543 |
|
|
|
| 544 |
|
|
================================================================================
|
| 545 |
|
|
Timing constraint: TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 10 ns HIGH 50%;
|
| 546 |
|
|
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
|
| 547 |
|
|
|
| 548 |
|
|
22 paths analyzed, 22 endpoints analyzed, 0 failing endpoints
|
| 549 |
|
|
|
| 550 |
|
|
Minimum period is 3.204ns.
|
| 551 |
|
|
--------------------------------------------------------------------------------
|
| 552 |
|
|
|
| 553 |
|
|
Paths for end point wb_interface/rxreg_20 (SLICE_X1Y54.CE), 1 path
|
| 554 |
|
|
--------------------------------------------------------------------------------
|
| 555 |
|
|
Slack (setup path): 6.860ns (requirement - (data path - clock path skew + uncertainty))
|
| 556 |
|
|
Source: wb_interface/rxreg_20 (FF)
|
| 557 |
|
|
Destination: wb_interface/rxreg_20 (FF)
|
| 558 |
|
|
Requirement: 10.000ns
|
| 559 |
|
|
Data Path Delay: 3.140ns (Levels of Logic = 1)
|
| 560 |
|
|
Clock Path Skew: 0.000ns
|
| 561 |
|
|
Source Clock: wb_clk_i_BUFGP falling at 5.000ns
|
| 562 |
|
|
Destination Clock: wb_clk_i_BUFGP falling at 15.000ns
|
| 563 |
|
|
Clock Uncertainty: 0.000ns
|
| 564 |
|
|
|
| 565 |
|
|
Maximum Data Path: wb_interface/rxreg_20 to wb_interface/rxreg_20
|
| 566 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 567 |
|
|
Logical Resource(s)
|
| 568 |
|
|
------------------------------------------------- -------------------
|
| 569 |
|
|
SLICE_X1Y54.XQ Tcko 0.591 wb_interface/rxreg<20>
|
| 570 |
|
|
wb_interface/rxreg_20
|
| 571 |
|
|
SLICE_X0Y54.G4 net (fanout=1) 0.404 wb_interface/rxreg<20>
|
| 572 |
|
|
SLICE_X0Y54.Y Tilo 0.707 wb_interface/wb_dat_rdbk
|
| 573 |
|
|
wb_interface/rxreg_and00001
|
| 574 |
|
|
SLICE_X1Y54.CE net (fanout=2) 1.127 wb_interface/rxreg_and0000
|
| 575 |
|
|
SLICE_X1Y54.CLK Tceck 0.311 wb_interface/rxreg<20>
|
| 576 |
|
|
wb_interface/rxreg_20
|
| 577 |
|
|
------------------------------------------------- ---------------------------
|
| 578 |
|
|
Total 3.140ns (1.609ns logic, 1.531ns route)
|
| 579 |
|
|
(51.2% logic, 48.8% route)
|
| 580 |
|
|
|
| 581 |
|
|
--------------------------------------------------------------------------------
|
| 582 |
|
|
|
| 583 |
|
|
Paths for end point wb_interface/rxreg_17 (SLICE_X1Y54.CE), 1 path
|
| 584 |
|
|
--------------------------------------------------------------------------------
|
| 585 |
|
|
Slack (setup path): 6.860ns (requirement - (data path - clock path skew + uncertainty))
|
| 586 |
|
|
Source: wb_interface/rxreg_20 (FF)
|
| 587 |
|
|
Destination: wb_interface/rxreg_17 (FF)
|
| 588 |
|
|
Requirement: 10.000ns
|
| 589 |
|
|
Data Path Delay: 3.140ns (Levels of Logic = 1)
|
| 590 |
|
|
Clock Path Skew: 0.000ns
|
| 591 |
|
|
Source Clock: wb_clk_i_BUFGP falling at 5.000ns
|
| 592 |
|
|
Destination Clock: wb_clk_i_BUFGP falling at 15.000ns
|
| 593 |
|
|
Clock Uncertainty: 0.000ns
|
| 594 |
|
|
|
| 595 |
|
|
Maximum Data Path: wb_interface/rxreg_20 to wb_interface/rxreg_17
|
| 596 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 597 |
|
|
Logical Resource(s)
|
| 598 |
|
|
------------------------------------------------- -------------------
|
| 599 |
|
|
SLICE_X1Y54.XQ Tcko 0.591 wb_interface/rxreg<20>
|
| 600 |
|
|
wb_interface/rxreg_20
|
| 601 |
|
|
SLICE_X0Y54.G4 net (fanout=1) 0.404 wb_interface/rxreg<20>
|
| 602 |
|
|
SLICE_X0Y54.Y Tilo 0.707 wb_interface/wb_dat_rdbk
|
| 603 |
|
|
wb_interface/rxreg_and00001
|
| 604 |
|
|
SLICE_X1Y54.CE net (fanout=2) 1.127 wb_interface/rxreg_and0000
|
| 605 |
|
|
SLICE_X1Y54.CLK Tceck 0.311 wb_interface/rxreg<20>
|
| 606 |
|
|
wb_interface/rxreg_17
|
| 607 |
|
|
------------------------------------------------- ---------------------------
|
| 608 |
|
|
Total 3.140ns (1.609ns logic, 1.531ns route)
|
| 609 |
|
|
(51.2% logic, 48.8% route)
|
| 610 |
|
|
|
| 611 |
|
|
--------------------------------------------------------------------------------
|
| 612 |
|
|
|
| 613 |
|
|
Paths for end point wb_interface/rxreg_15 (SLICE_X1Y50.CE), 1 path
|
| 614 |
|
|
--------------------------------------------------------------------------------
|
| 615 |
|
|
Slack (setup path): 6.861ns (requirement - (data path - clock path skew + uncertainty))
|
| 616 |
|
|
Source: wb_interface/rxreg_20 (FF)
|
| 617 |
|
|
Destination: wb_interface/rxreg_15 (FF)
|
| 618 |
|
|
Requirement: 10.000ns
|
| 619 |
|
|
Data Path Delay: 3.140ns (Levels of Logic = 1)
|
| 620 |
|
|
Clock Path Skew: 0.001ns (0.020 - 0.019)
|
| 621 |
|
|
Source Clock: wb_clk_i_BUFGP falling at 5.000ns
|
| 622 |
|
|
Destination Clock: wb_clk_i_BUFGP falling at 15.000ns
|
| 623 |
|
|
Clock Uncertainty: 0.000ns
|
| 624 |
|
|
|
| 625 |
|
|
Maximum Data Path: wb_interface/rxreg_20 to wb_interface/rxreg_15
|
| 626 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 627 |
|
|
Logical Resource(s)
|
| 628 |
|
|
------------------------------------------------- -------------------
|
| 629 |
|
|
SLICE_X1Y54.XQ Tcko 0.591 wb_interface/rxreg<20>
|
| 630 |
|
|
wb_interface/rxreg_20
|
| 631 |
|
|
SLICE_X0Y54.G4 net (fanout=1) 0.404 wb_interface/rxreg<20>
|
| 632 |
|
|
SLICE_X0Y54.Y Tilo 0.707 wb_interface/wb_dat_rdbk
|
| 633 |
|
|
wb_interface/rxreg_and00001
|
| 634 |
|
|
SLICE_X1Y50.CE net (fanout=2) 1.127 wb_interface/rxreg_and0000
|
| 635 |
|
|
SLICE_X1Y50.CLK Tceck 0.311 wb_interface/rxreg<15>
|
| 636 |
|
|
wb_interface/rxreg_15
|
| 637 |
|
|
------------------------------------------------- ---------------------------
|
| 638 |
|
|
Total 3.140ns (1.609ns logic, 1.531ns route)
|
| 639 |
|
|
(51.2% logic, 48.8% route)
|
| 640 |
|
|
|
| 641 |
|
|
--------------------------------------------------------------------------------
|
| 642 |
|
|
|
| 643 |
|
|
Hold Paths: TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 10 ns HIGH 50%;
|
| 644 |
|
|
--------------------------------------------------------------------------------
|
| 645 |
|
|
|
| 646 |
|
|
Paths for end point wb_interface/txreg_20 (SLICE_X0Y56.CE), 1 path
|
| 647 |
|
|
--------------------------------------------------------------------------------
|
| 648 |
|
|
Slack (hold path): 1.912ns (requirement - (clock path skew + uncertainty - data path))
|
| 649 |
|
|
Source: wb_interface/txreg_20 (FF)
|
| 650 |
|
|
Destination: wb_interface/txreg_20 (FF)
|
| 651 |
|
|
Requirement: 0.000ns
|
| 652 |
|
|
Data Path Delay: 1.912ns (Levels of Logic = 1)
|
| 653 |
|
|
Clock Path Skew: 0.000ns
|
| 654 |
|
|
Source Clock: wb_clk_i_BUFGP falling at 15.000ns
|
| 655 |
|
|
Destination Clock: wb_clk_i_BUFGP falling at 15.000ns
|
| 656 |
|
|
Clock Uncertainty: 0.000ns
|
| 657 |
|
|
|
| 658 |
|
|
Minimum Data Path: wb_interface/txreg_20 to wb_interface/txreg_20
|
| 659 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 660 |
|
|
Logical Resource(s)
|
| 661 |
|
|
------------------------------------------------- -------------------
|
| 662 |
|
|
SLICE_X0Y56.XQ Tcko 0.505 wb_interface/txreg<20>
|
| 663 |
|
|
wb_interface/txreg_20
|
| 664 |
|
|
SLICE_X1Y56.F1 net (fanout=1) 0.377 wb_interface/txreg<20>
|
| 665 |
|
|
SLICE_X1Y56.X Tilo 0.514 wb_interface/txreg_and0000
|
| 666 |
|
|
wb_interface/txreg_and00001
|
| 667 |
|
|
SLICE_X0Y56.CE net (fanout=9) 0.516 wb_interface/txreg_and0000
|
| 668 |
|
|
SLICE_X0Y56.CLK Tckce (-Th) 0.000 wb_interface/txreg<20>
|
| 669 |
|
|
wb_interface/txreg_20
|
| 670 |
|
|
------------------------------------------------- ---------------------------
|
| 671 |
|
|
Total 1.912ns (1.019ns logic, 0.893ns route)
|
| 672 |
|
|
(53.3% logic, 46.7% route)
|
| 673 |
|
|
|
| 674 |
|
|
--------------------------------------------------------------------------------
|
| 675 |
|
|
|
| 676 |
|
|
Paths for end point wb_interface/txreg_17 (SLICE_X0Y56.CE), 1 path
|
| 677 |
|
|
--------------------------------------------------------------------------------
|
| 678 |
|
|
Slack (hold path): 1.912ns (requirement - (clock path skew + uncertainty - data path))
|
| 679 |
|
|
Source: wb_interface/txreg_20 (FF)
|
| 680 |
|
|
Destination: wb_interface/txreg_17 (FF)
|
| 681 |
|
|
Requirement: 0.000ns
|
| 682 |
|
|
Data Path Delay: 1.912ns (Levels of Logic = 1)
|
| 683 |
|
|
Clock Path Skew: 0.000ns
|
| 684 |
|
|
Source Clock: wb_clk_i_BUFGP falling at 15.000ns
|
| 685 |
|
|
Destination Clock: wb_clk_i_BUFGP falling at 15.000ns
|
| 686 |
|
|
Clock Uncertainty: 0.000ns
|
| 687 |
|
|
|
| 688 |
|
|
Minimum Data Path: wb_interface/txreg_20 to wb_interface/txreg_17
|
| 689 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 690 |
|
|
Logical Resource(s)
|
| 691 |
|
|
------------------------------------------------- -------------------
|
| 692 |
|
|
SLICE_X0Y56.XQ Tcko 0.505 wb_interface/txreg<20>
|
| 693 |
|
|
wb_interface/txreg_20
|
| 694 |
|
|
SLICE_X1Y56.F1 net (fanout=1) 0.377 wb_interface/txreg<20>
|
| 695 |
|
|
SLICE_X1Y56.X Tilo 0.514 wb_interface/txreg_and0000
|
| 696 |
|
|
wb_interface/txreg_and00001
|
| 697 |
|
|
SLICE_X0Y56.CE net (fanout=9) 0.516 wb_interface/txreg_and0000
|
| 698 |
|
|
SLICE_X0Y56.CLK Tckce (-Th) 0.000 wb_interface/txreg<20>
|
| 699 |
|
|
wb_interface/txreg_17
|
| 700 |
|
|
------------------------------------------------- ---------------------------
|
| 701 |
|
|
Total 1.912ns (1.019ns logic, 0.893ns route)
|
| 702 |
|
|
(53.3% logic, 46.7% route)
|
| 703 |
|
|
|
| 704 |
|
|
--------------------------------------------------------------------------------
|
| 705 |
|
|
|
| 706 |
|
|
Paths for end point wb_interface/txreg_5 (SLICE_X3Y47.CE), 1 path
|
| 707 |
|
|
--------------------------------------------------------------------------------
|
| 708 |
|
|
Slack (hold path): 1.944ns (requirement - (clock path skew + uncertainty - data path))
|
| 709 |
|
|
Source: wb_interface/txreg_20 (FF)
|
| 710 |
|
|
Destination: wb_interface/txreg_5 (FF)
|
| 711 |
|
|
Requirement: 0.000ns
|
| 712 |
|
|
Data Path Delay: 2.094ns (Levels of Logic = 1)
|
| 713 |
|
|
Clock Path Skew: 0.150ns (0.749 - 0.599)
|
| 714 |
|
|
Source Clock: wb_clk_i_BUFGP falling at 15.000ns
|
| 715 |
|
|
Destination Clock: wb_clk_i_BUFGP falling at 15.000ns
|
| 716 |
|
|
Clock Uncertainty: 0.000ns
|
| 717 |
|
|
|
| 718 |
|
|
Minimum Data Path: wb_interface/txreg_20 to wb_interface/txreg_5
|
| 719 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 720 |
|
|
Logical Resource(s)
|
| 721 |
|
|
------------------------------------------------- -------------------
|
| 722 |
|
|
SLICE_X0Y56.XQ Tcko 0.505 wb_interface/txreg<20>
|
| 723 |
|
|
wb_interface/txreg_20
|
| 724 |
|
|
SLICE_X1Y56.F1 net (fanout=1) 0.377 wb_interface/txreg<20>
|
| 725 |
|
|
SLICE_X1Y56.X Tilo 0.514 wb_interface/txreg_and0000
|
| 726 |
|
|
wb_interface/txreg_and00001
|
| 727 |
|
|
SLICE_X3Y47.CE net (fanout=9) 0.698 wb_interface/txreg_and0000
|
| 728 |
|
|
SLICE_X3Y47.CLK Tckce (-Th) 0.000 wb_interface/txreg<5>
|
| 729 |
|
|
wb_interface/txreg_5
|
| 730 |
|
|
------------------------------------------------- ---------------------------
|
| 731 |
|
|
Total 2.094ns (1.019ns logic, 1.075ns route)
|
| 732 |
|
|
(48.7% logic, 51.3% route)
|
| 733 |
|
|
|
| 734 |
|
|
--------------------------------------------------------------------------------
|
| 735 |
|
|
|
| 736 |
|
|
Component Switching Limit Checks: TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 10 ns HIGH 50%;
|
| 737 |
|
|
--------------------------------------------------------------------------------
|
| 738 |
|
|
Slack: 6.796ns (period - (min low pulse limit / (low pulse / period)))
|
| 739 |
|
|
Period: 10.000ns
|
| 740 |
|
|
Low pulse: 5.000ns
|
| 741 |
|
|
Low pulse limit: 1.602ns (Trpw)
|
| 742 |
|
|
Physical resource: wb_interface/txreg<1>/SR
|
| 743 |
|
|
Logical resource: wb_interface/txreg_1/SR
|
| 744 |
|
|
Location pin: SLICE_X2Y51.SR
|
| 745 |
|
|
Clock network: wb_rst_i_IBUF
|
| 746 |
|
|
--------------------------------------------------------------------------------
|
| 747 |
|
|
Slack: 6.796ns (period - (min high pulse limit / (high pulse / period)))
|
| 748 |
|
|
Period: 10.000ns
|
| 749 |
|
|
High pulse: 5.000ns
|
| 750 |
|
|
High pulse limit: 1.602ns (Trpw)
|
| 751 |
|
|
Physical resource: wb_interface/txreg<1>/SR
|
| 752 |
|
|
Logical resource: wb_interface/txreg_1/SR
|
| 753 |
|
|
Location pin: SLICE_X2Y51.SR
|
| 754 |
|
|
Clock network: wb_rst_i_IBUF
|
| 755 |
|
|
--------------------------------------------------------------------------------
|
| 756 |
|
|
Slack: 6.796ns (period - (min low pulse limit / (low pulse / period)))
|
| 757 |
|
|
Period: 10.000ns
|
| 758 |
|
|
Low pulse: 5.000ns
|
| 759 |
|
|
Low pulse limit: 1.602ns (Trpw)
|
| 760 |
|
|
Physical resource: wb_interface/txreg<1>/SR
|
| 761 |
|
|
Logical resource: wb_interface/txreg_0/SR
|
| 762 |
|
|
Location pin: SLICE_X2Y51.SR
|
| 763 |
|
|
Clock network: wb_rst_i_IBUF
|
| 764 |
|
|
--------------------------------------------------------------------------------
|
| 765 |
|
|
|
| 766 |
|
|
|
| 767 |
|
|
All constraints were met.
|
| 768 |
|
|
|
| 769 |
|
|
|
| 770 |
|
|
Data Sheet report:
|
| 771 |
|
|
-----------------
|
| 772 |
|
|
All values displayed in nanoseconds (ns)
|
| 773 |
|
|
|
| 774 |
|
|
Clock to Setup on destination clock txclk
|
| 775 |
|
|
---------------+---------+---------+---------+---------+
|
| 776 |
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
| 777 |
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
| 778 |
|
|
---------------+---------+---------+---------+---------+
|
| 779 |
|
|
txclk | 4.635| | | |
|
| 780 |
|
|
---------------+---------+---------+---------+---------+
|
| 781 |
|
|
|
| 782 |
|
|
Clock to Setup on destination clock wb_clk_i
|
| 783 |
|
|
---------------+---------+---------+---------+---------+
|
| 784 |
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
| 785 |
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
| 786 |
|
|
---------------+---------+---------+---------+---------+
|
| 787 |
|
|
wb_clk_i | | | | 3.140|
|
| 788 |
|
|
---------------+---------+---------+---------+---------+
|
| 789 |
|
|
|
| 790 |
|
|
|
| 791 |
|
|
Timing summary:
|
| 792 |
|
|
---------------
|
| 793 |
|
|
|
| 794 |
|
|
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
|
| 795 |
|
|
|
| 796 |
|
|
Constraints cover 150 paths, 0 nets, and 140 connections
|
| 797 |
|
|
|
| 798 |
|
|
Design statistics:
|
| 799 |
|
|
Minimum period: 4.635ns{1} (Maximum frequency: 215.750MHz)
|
| 800 |
|
|
|
| 801 |
|
|
|
| 802 |
|
|
------------------------------------Footnotes-----------------------------------
|
| 803 |
|
|
1) The minimum period statistic assumes all single cycle delays.
|
| 804 |
|
|
|
| 805 |
|
|
Analysis completed Fri Feb 20 14:09:29 2015
|
| 806 |
|
|
--------------------------------------------------------------------------------
|
| 807 |
|
|
|
| 808 |
|
|
Trace Settings:
|
| 809 |
|
|
-------------------------
|
| 810 |
|
|
Trace Settings
|
| 811 |
|
|
|
| 812 |
|
|
Peak Memory Usage: 188 MB
|
| 813 |
|
|
|
| 814 |
|
|
|
| 815 |
|
|
|
