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jeaander |
#-----------------------------------------------------------
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# Vivado v2014.2 (64-bit)
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# SW Build 932637 on Wed Jun 11 13:33:10 MDT 2014
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# IP Build 924643 on Fri May 30 09:20:16 MDT 2014
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# Start of session at: Fri Feb 20 14:22:29 2015
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# Process ID: 3032
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# Log file: C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/vivado/sport_top/sport_top.runs/synth_1/sport_top.vds
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# Journal file: C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/vivado/sport_top/sport_top.runs/synth_1\vivado.jou
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#-----------------------------------------------------------
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source sport_top.tcl
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# set_param gui.test TreeTableDev
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# set_msg_config -id {HDL 9-1061} -limit 100000
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# set_msg_config -id {HDL 9-1654} -limit 100000
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# create_project -in_memory -part xc7vx485tffg1157-1
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# set_property target_language Verilog [current_project]
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# set_param project.compositeFile.enableAutoGeneration 0
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# set_property default_lib xil_defaultlib [current_project]
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# read_verilog C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_defines.v
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# set_property file_type "Verilog Header" [get_files C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_defines.v]
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# read_verilog -library xil_defaultlib {
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# C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v
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# C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/fifos.v
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# C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v
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# }
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WARNING: [filemgmt 20-1763] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v]
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WARNING: [filemgmt 20-1763] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/fifos.v]
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WARNING: [filemgmt 20-1763] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v]
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# read_xdc C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/vivado/sport_top/sport_top.srcs/constrs_1/new/sport_top.xdc
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# set_property used_in_implementation false [get_files C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/vivado/sport_top/sport_top.srcs/constrs_1/new/sport_top.xdc]
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# set_param synth.vivado.isSynthRun true
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# set_property webtalk.parent_dir C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/vivado/sport_top/sport_top.cache/wt [current_project]
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# set_property parent.project_dir C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/vivado/sport_top [current_project]
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# catch { write_hwdef -file sport_top.hwdef }
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INFO: [Vivado_Tcl 4-279] hardware handoff file cannot be generated as there is no block diagram instance in the design
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# synth_design -top sport_top -part xc7vx485tffg1157-1
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Command: synth_design -top sport_top -part xc7vx485tffg1157-1
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Starting synthesis...
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx485t'
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WARNING: [Common 17-348] Failed to get the license for feature 'Synthesis' and/or device 'xc7vx485t'
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synth_design failed
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ERROR: [Common 17-345] A valid license was not found for feature 'Synthesis' and/or device 'xc7vx485t'. Please run the Vivado License Manager for assistance in determining
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which features and devices are licensed for your system.
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Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ".
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while executing
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"synth_design -top sport_top -part xc7vx485tffg1157-1"
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(file "sport_top.tcl" line 26)
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INFO: [Common 17-206] Exiting Vivado at Fri Feb 20 14:22:32 2015...
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