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Example Bridge / Switching Hub
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The bridge directory contains an example bridge built using
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srdy-drdy components. It could more accurately be called
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a switching hub, since it does not implement spanning tree
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or QoS.
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The bridge is designed for simplicity rather than efficiency,
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as the purpose is not to make a functioning product but to
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demonstrate use of the library.
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The bridge design pushes the bulk of the logic into each
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individual port, called a port_macro. The only global logic
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is the FIB (Forwarding Information Block) that contains the
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address lookup and learning logic, and a centralized ring
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arbiter.
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The port_macros are connected to each other via a ring interface.
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Only one packet can be transmitted on the ring at a time.
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The system is designed so that it has more ring bandwidth than
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the maximum amount of incoming traffic, so that the ring should
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not be the bottleneck for system performance.
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The bridge is designed to be output-queued, so that all packets
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are forwarded to their output port and the output port will
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drop packets if there is insufficient transmit bandwidth.
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The bridge handles all transmission errors on the input port,
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using the rx_fifo to drop packets which arrive with bad CRC.
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The parser waits until the end of packet is received to determine
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if the packet is good, and only sends the packet to the FIB
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if CRC is OK. Otherwise the parser errors the packet so it
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will be dropped in RX FIFO.
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Packets are transmitted and received using an 8-bit GMII interface.
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In order to create a higher-bandwidth internal interface, data
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is aggregated into 64-bit words to get 8x bandwidth. This gives
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the internal ring roughly 2x the bandwidth of all receiving ports
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combined.
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