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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [bridge.vh] - Blame information for rev 5

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Line No. Rev Author Line
1 4 ghutchis
 
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// Address size for number of ports.  Default value 4,
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// which will allow design to scale up to 16 ports
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`define PORT_ASZ    4
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// We will have only 4 ports in our sample design
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`define NUM_PORTS   4
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// Data structure from parser to FIB.  Contains MAC DA,
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// MAC SA, and source port
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`define PAR_DATA_SZ (48+48+4)
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`define PAR_MACDA    47:0
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`define PAR_MACSA    95:48
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`define PAR_SRCPORT  99:96
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// number of entries in FIB table
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`define FIB_ENTRIES   256
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`define FIB_ASZ       $clog2(`FIB_ENTRIES)
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// FIB entry definition
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`define FIB_ENTRY_SZ  60
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`define FIB_MACADDR   47:0     // MAC address
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`define FIB_AGE       55:48    // 8 bit age counter
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`define FIB_PORT      59:56    // associated port
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`define FIB_MAX_AGE   255      // maximum value of age timer
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28 5 ghutchis
`define MULTICAST     48'h0100000000  // multicast bit
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// Packet control codes
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`define PCC_SOP     2'b01    // Start of packet
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`define PCC_DATA    2'b00    // data word
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`define PCC_EOP     2'b10    // End of packet
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`define PCC_BADEOP  2'b11    // End of packet w/ error
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// Packet Ring Word
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`define PRW_SZ       70
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`define PRW_DATA     63:0      // 64 bits of packet data
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`define PRW_PCC      65:64     // packet control code
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`define PRW_VALID    68:66     // # of valid bytes modulo 8
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`define PRW_PVEC     69        // indicates this is port vector word

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