1 |
8 |
ghutchis |
// Top level for bridge example
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//
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// 4-port bridge has 4 GMII interfaces, each one of which has its own RX clock
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// Port macros contain all packet buffering, and ring interface to communicate
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// with other port macros.
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// FIB block receives requests from all ports and sends results back to the
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// same port containing forwarding information.
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module bridge_ex1
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(input clk,
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input reset,
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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ghutchis |
input gmii_rx_clk_0, // To p0 of port_macro.v
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input gmii_rx_clk_1, // To p1 of port_macro.v
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input gmii_rx_clk_2, // To p2 of port_macro.v
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input gmii_rx_clk_3, // To p3 of port_macro.v
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input gmii_rx_dv_0, // To p0 of port_macro.v
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input gmii_rx_dv_1, // To p1 of port_macro.v
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input gmii_rx_dv_2, // To p2 of port_macro.v
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input gmii_rx_dv_3, // To p3 of port_macro.v
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input [7:0] gmii_rxd_0, // To p0 of port_macro.v
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input [7:0] gmii_rxd_1, // To p1 of port_macro.v
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input [7:0] gmii_rxd_2, // To p2 of port_macro.v
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input [7:0] gmii_rxd_3, // To p3 of port_macro.v
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8 |
ghutchis |
// End of automatics
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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ghutchis |
output gmii_tx_en_0, // From p0 of port_macro.v
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output gmii_tx_en_1, // From p1 of port_macro.v
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output gmii_tx_en_2, // From p2 of port_macro.v
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output gmii_tx_en_3, // From p3 of port_macro.v
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output [7:0] gmii_txd_0, // From p0 of port_macro.v
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output [7:0] gmii_txd_1, // From p1 of port_macro.v
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output [7:0] gmii_txd_2, // From p2 of port_macro.v
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output [7:0] gmii_txd_3 // From p3 of port_macro.v
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ghutchis |
// End of automatics
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);
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wire [`PRW_SZ-1:0] ri_data_0;
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wire [`PRW_SZ-1:0] ri_data_1;
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wire [`PRW_SZ-1:0] ri_data_2;
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wire [`PRW_SZ-1:0] ri_data_3;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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ghutchis |
wire [`NUM_PORTS-1:0] flo_data; // From fib_lookup of fib_lookup.v
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wire [3:0] flo_drdy; // From p0 of port_macro.v, ...
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wire [`NUM_PORTS-1:0] flo_srdy; // From fib_lookup of fib_lookup.v
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wire [`PAR_DATA_SZ-1:0] p2f_data_0; // From p0 of port_macro.v
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wire [`PAR_DATA_SZ-1:0] p2f_data_1; // From p1 of port_macro.v
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wire [`PAR_DATA_SZ-1:0] p2f_data_2; // From p2 of port_macro.v
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wire [`PAR_DATA_SZ-1:0] p2f_data_3; // From p3 of port_macro.v
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ghutchis |
wire [`NUM_PORTS-1:0] p2f_drdy; // From fib_arb of sd_rrmux.v
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ghutchis |
wire [3:0] p2f_srdy; // From p0 of port_macro.v, ...
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ghutchis |
wire [`PAR_DATA_SZ-1:0] ppi_data; // From fib_arb of sd_rrmux.v
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ghutchis |
wire ppi_drdy; // From fib_lookup of fib_lookup.v
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ghutchis |
wire ppi_srdy; // From fib_arb of sd_rrmux.v
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ghutchis |
wire [`NUM_PORTS-1:0] rarb_ack; // From ring_arb of ring_arb.v
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wire [3:0] rarb_req; // From p0 of port_macro.v, ...
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ghutchis |
wire ri_drdy_0; // From p0 of port_macro.v
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wire ri_drdy_1; // From p1 of port_macro.v
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wire ri_drdy_2; // From p2 of port_macro.v
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wire ri_drdy_3; // From p3 of port_macro.v
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wire ri_srdy_0; // From p3 of port_macro.v
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wire ri_srdy_1; // From p0 of port_macro.v
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wire ri_srdy_2; // From p1 of port_macro.v
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wire ri_srdy_3; // From p2 of port_macro.v
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ghutchis |
// End of automatics
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/* port_macro AUTO_TEMPLATE
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(
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.clk (clk),
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.reset (reset),
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.ri_data (ri_data_@),
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ghutchis |
.rarb_\(.*\) (rarb_\1[@]),
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ghutchis |
.ro_\(.*\) (ri_\1_@"(% (+ 1 @) 4)"),
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.p2f_srdy (p2f_srdy[@]),
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.p2f_drdy (p2f_drdy[@]),
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.fli_srdy (flo_srdy[@]),
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.fli_drdy (flo_drdy[@]),
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.fli_data (flo_data),
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.\(.*\) (\1_@[]),
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);
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*/
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ghutchis |
port_macro #(0) p0
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ghutchis |
(/*AUTOINST*/
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// Outputs
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ghutchis |
.ro_data (ri_data_1), // Templated
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ghutchis |
.rarb_req (rarb_req[0]), // Templated
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ghutchis |
.fli_drdy (flo_drdy[0]), // Templated
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.gmii_tx_en (gmii_tx_en_0), // Templated
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.gmii_txd (gmii_txd_0[7:0]), // Templated
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.p2f_data (p2f_data_0[`PAR_DATA_SZ-1:0]), // Templated
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.p2f_srdy (p2f_srdy[0]), // Templated
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.ri_drdy (ri_drdy_0), // Templated
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.ro_srdy (ri_srdy_1), // Templated
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ghutchis |
// Inputs
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ghutchis |
.clk (clk), // Templated
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.reset (reset), // Templated
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.ri_data (ri_data_0), // Templated
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.fli_data (flo_data), // Templated
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.fli_srdy (flo_srdy[0]), // Templated
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.gmii_rx_clk (gmii_rx_clk_0), // Templated
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.gmii_rx_dv (gmii_rx_dv_0), // Templated
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.gmii_rxd (gmii_rxd_0[7:0]), // Templated
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.p2f_drdy (p2f_drdy[0]), // Templated
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12 |
ghutchis |
.rarb_ack (rarb_ack[0]), // Templated
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ghutchis |
.ri_srdy (ri_srdy_0), // Templated
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.ro_drdy (ri_drdy_1)); // Templated
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8 |
ghutchis |
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11 |
ghutchis |
port_macro #(1) p1
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8 |
ghutchis |
(/*AUTOINST*/
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// Outputs
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ghutchis |
.ro_data (ri_data_2), // Templated
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12 |
ghutchis |
.rarb_req (rarb_req[1]), // Templated
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11 |
ghutchis |
.fli_drdy (flo_drdy[1]), // Templated
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.gmii_tx_en (gmii_tx_en_1), // Templated
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.gmii_txd (gmii_txd_1[7:0]), // Templated
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.p2f_data (p2f_data_1[`PAR_DATA_SZ-1:0]), // Templated
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.p2f_srdy (p2f_srdy[1]), // Templated
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.ri_drdy (ri_drdy_1), // Templated
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.ro_srdy (ri_srdy_2), // Templated
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ghutchis |
// Inputs
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11 |
ghutchis |
.clk (clk), // Templated
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.reset (reset), // Templated
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.ri_data (ri_data_1), // Templated
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.fli_data (flo_data), // Templated
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.fli_srdy (flo_srdy[1]), // Templated
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.gmii_rx_clk (gmii_rx_clk_1), // Templated
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.gmii_rx_dv (gmii_rx_dv_1), // Templated
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.gmii_rxd (gmii_rxd_1[7:0]), // Templated
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.p2f_drdy (p2f_drdy[1]), // Templated
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12 |
ghutchis |
.rarb_ack (rarb_ack[1]), // Templated
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11 |
ghutchis |
.ri_srdy (ri_srdy_1), // Templated
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.ro_drdy (ri_drdy_2)); // Templated
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ghutchis |
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ghutchis |
port_macro #(2) p2
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ghutchis |
(/*AUTOINST*/
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// Outputs
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ghutchis |
.ro_data (ri_data_3), // Templated
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12 |
ghutchis |
.rarb_req (rarb_req[2]), // Templated
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11 |
ghutchis |
.fli_drdy (flo_drdy[2]), // Templated
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.gmii_tx_en (gmii_tx_en_2), // Templated
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.gmii_txd (gmii_txd_2[7:0]), // Templated
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.p2f_data (p2f_data_2[`PAR_DATA_SZ-1:0]), // Templated
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.p2f_srdy (p2f_srdy[2]), // Templated
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.ri_drdy (ri_drdy_2), // Templated
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.ro_srdy (ri_srdy_3), // Templated
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8 |
ghutchis |
// Inputs
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150 |
11 |
ghutchis |
.clk (clk), // Templated
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151 |
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.reset (reset), // Templated
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.ri_data (ri_data_2), // Templated
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153 |
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.fli_data (flo_data), // Templated
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.fli_srdy (flo_srdy[2]), // Templated
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.gmii_rx_clk (gmii_rx_clk_2), // Templated
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.gmii_rx_dv (gmii_rx_dv_2), // Templated
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.gmii_rxd (gmii_rxd_2[7:0]), // Templated
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158 |
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.p2f_drdy (p2f_drdy[2]), // Templated
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12 |
ghutchis |
.rarb_ack (rarb_ack[2]), // Templated
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160 |
11 |
ghutchis |
.ri_srdy (ri_srdy_2), // Templated
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161 |
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.ro_drdy (ri_drdy_3)); // Templated
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8 |
ghutchis |
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11 |
ghutchis |
port_macro #(3) p3
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164 |
8 |
ghutchis |
(/*AUTOINST*/
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165 |
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// Outputs
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166 |
11 |
ghutchis |
.ro_data (ri_data_0), // Templated
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167 |
12 |
ghutchis |
.rarb_req (rarb_req[3]), // Templated
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168 |
11 |
ghutchis |
.fli_drdy (flo_drdy[3]), // Templated
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169 |
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.gmii_tx_en (gmii_tx_en_3), // Templated
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170 |
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.gmii_txd (gmii_txd_3[7:0]), // Templated
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171 |
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.p2f_data (p2f_data_3[`PAR_DATA_SZ-1:0]), // Templated
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172 |
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.p2f_srdy (p2f_srdy[3]), // Templated
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173 |
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.ri_drdy (ri_drdy_3), // Templated
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174 |
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.ro_srdy (ri_srdy_0), // Templated
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175 |
8 |
ghutchis |
// Inputs
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176 |
11 |
ghutchis |
.clk (clk), // Templated
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177 |
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.reset (reset), // Templated
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178 |
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.ri_data (ri_data_3), // Templated
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179 |
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.fli_data (flo_data), // Templated
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180 |
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.fli_srdy (flo_srdy[3]), // Templated
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181 |
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.gmii_rx_clk (gmii_rx_clk_3), // Templated
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182 |
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.gmii_rx_dv (gmii_rx_dv_3), // Templated
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183 |
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.gmii_rxd (gmii_rxd_3[7:0]), // Templated
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184 |
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.p2f_drdy (p2f_drdy[3]), // Templated
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185 |
12 |
ghutchis |
.rarb_ack (rarb_ack[3]), // Templated
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186 |
11 |
ghutchis |
.ri_srdy (ri_srdy_3), // Templated
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187 |
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.ro_drdy (ri_drdy_0)); // Templated
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188 |
8 |
ghutchis |
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189 |
21 |
ghutchis |
/* sd_rrmux AUTO_TEMPLATE
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190 |
8 |
ghutchis |
(
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191 |
21 |
ghutchis |
.p_grant (),
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192 |
8 |
ghutchis |
.p_data (ppi_data[`PAR_DATA_SZ-1:0]),
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193 |
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.c_data ({p2f_data_3,p2f_data_2,p2f_data_1,p2f_data_0}),
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194 |
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.c_srdy (p2f_srdy[`NUM_PORTS-1:0]),
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195 |
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.c_drdy (p2f_drdy[`NUM_PORTS-1:0]),
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196 |
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.c_\(.*\) (p2f_\1[]),
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197 |
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.p_\(.*\) (ppi_\1[]),
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198 |
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);
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199 |
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*/
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200 |
21 |
ghutchis |
sd_rrmux #(
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201 |
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// Parameters
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202 |
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.width (`PAR_DATA_SZ),
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203 |
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.inputs (`NUM_PORTS),
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204 |
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.mode (0),
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205 |
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.fast_arb (1)) fib_arb
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206 |
8 |
ghutchis |
(/*AUTOINST*/
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207 |
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// Outputs
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208 |
11 |
ghutchis |
.c_drdy (p2f_drdy[`NUM_PORTS-1:0]), // Templated
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209 |
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.p_data (ppi_data[`PAR_DATA_SZ-1:0]), // Templated
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210 |
21 |
ghutchis |
.p_grant (), // Templated
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211 |
11 |
ghutchis |
.p_srdy (ppi_srdy), // Templated
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212 |
8 |
ghutchis |
// Inputs
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213 |
11 |
ghutchis |
.clk (clk),
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214 |
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.reset (reset),
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215 |
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.c_data ({p2f_data_3,p2f_data_2,p2f_data_1,p2f_data_0}), // Templated
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216 |
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.c_srdy (p2f_srdy[`NUM_PORTS-1:0]), // Templated
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217 |
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.p_drdy (ppi_drdy)); // Templated
|
218 |
8 |
ghutchis |
|
219 |
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fib_lookup fib_lookup
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220 |
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(/*AUTOINST*/
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221 |
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// Outputs
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222 |
11 |
ghutchis |
.flo_data (flo_data[`NUM_PORTS-1:0]),
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223 |
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.flo_srdy (flo_srdy[`NUM_PORTS-1:0]),
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224 |
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.ppi_drdy (ppi_drdy),
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225 |
8 |
ghutchis |
// Inputs
|
226 |
11 |
ghutchis |
.clk (clk),
|
227 |
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.reset (reset),
|
228 |
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.ppi_data (ppi_data[`PAR_DATA_SZ-1:0]),
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229 |
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.flo_drdy (flo_drdy[`NUM_PORTS-1:0]),
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230 |
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.ppi_srdy (ppi_srdy));
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231 |
8 |
ghutchis |
|
232 |
12 |
ghutchis |
ring_arb ring_arb
|
233 |
|
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(/*AUTOINST*/
|
234 |
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// Outputs
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235 |
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.rarb_ack (rarb_ack[`NUM_PORTS-1:0]),
|
236 |
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// Inputs
|
237 |
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.clk (clk),
|
238 |
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.reset (reset),
|
239 |
|
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.rarb_req (rarb_req[`NUM_PORTS-1:0]));
|
240 |
|
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|
241 |
8 |
ghutchis |
endmodule // bridge_ex1
|
242 |
|
|
// Local Variables:
|
243 |
|
|
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/forks")
|
244 |
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// End:
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