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// Top level for bridge example
//
// 4-port bridge has 4 GMII interfaces, each one of which has its own RX clock
// Port macros contain all packet buffering, and ring interface to communicate
// with other port macros.
// FIB block receives requests from all ports and sends results back to the
// same port containing forwarding information.
 
module bridge_ex1
  (input  clk,
   input  reset,
   /*AUTOINPUT*/
   // Beginning of automatic inputs (from unused autoinst inputs)
   input                gmii_rx_clk_0,          // To p0 of port_macro.v
   input                gmii_rx_clk_1,          // To p1 of port_macro.v
   input                gmii_rx_clk_2,          // To p2 of port_macro.v
   input                gmii_rx_clk_3,          // To p3 of port_macro.v
   input                gmii_rx_dv_0,           // To p0 of port_macro.v
   input                gmii_rx_dv_1,           // To p1 of port_macro.v
   input                gmii_rx_dv_2,           // To p2 of port_macro.v
   input                gmii_rx_dv_3,           // To p3 of port_macro.v
   input [7:0]          gmii_rxd_0,             // To p0 of port_macro.v
   input [7:0]          gmii_rxd_1,             // To p1 of port_macro.v
   input [7:0]          gmii_rxd_2,             // To p2 of port_macro.v
   input [7:0]          gmii_rxd_3,             // To p3 of port_macro.v
   // End of automatics
   /*AUTOOUTPUT*/
   // Beginning of automatic outputs (from unused autoinst outputs)
   output               gmii_tx_en_0,           // From p0 of port_macro.v
   output               gmii_tx_en_1,           // From p1 of port_macro.v
   output               gmii_tx_en_2,           // From p2 of port_macro.v
   output               gmii_tx_en_3,           // From p3 of port_macro.v
   output [7:0]         gmii_txd_0,             // From p0 of port_macro.v
   output [7:0]         gmii_txd_1,             // From p1 of port_macro.v
   output [7:0]         gmii_txd_2,             // From p2 of port_macro.v
   output [7:0]         gmii_txd_3             // From p3 of port_macro.v
   // End of automatics
   );
 
  wire [`PRW_SZ-1:0]     ri_data_0;
  wire [`PRW_SZ-1:0]     ri_data_1;
  wire [`PRW_SZ-1:0]     ri_data_2;
  wire [`PRW_SZ-1:0]     ri_data_3;
  /*AUTOWIRE*/
  // Beginning of automatic wires (for undeclared instantiated-module outputs)
  wire [`NUM_PORTS-1:0] flo_data;               // From fib_lookup of fib_lookup.v
  wire [3:0]            flo_drdy;               // From p0 of port_macro.v, ...
  wire [`NUM_PORTS-1:0] flo_srdy;               // From fib_lookup of fib_lookup.v
  wire [`PAR_DATA_SZ-1:0] p2f_data_0;           // From p0 of port_macro.v
  wire [`PAR_DATA_SZ-1:0] p2f_data_1;           // From p1 of port_macro.v
  wire [`PAR_DATA_SZ-1:0] p2f_data_2;           // From p2 of port_macro.v
  wire [`PAR_DATA_SZ-1:0] p2f_data_3;           // From p3 of port_macro.v
  wire [`NUM_PORTS-1:0] p2f_drdy;               // From fib_arb of sd_rrslow.v
  wire [3:0]            p2f_srdy;               // From p0 of port_macro.v, ...
  wire [`PAR_DATA_SZ-1:0] ppi_data;             // From fib_arb of sd_rrslow.v
  wire                  ppi_drdy;               // From fib_lookup of fib_lookup.v
  wire                  ppi_srdy;               // From fib_arb of sd_rrslow.v
  wire                  ri_drdy_0;              // From p0 of port_macro.v
  wire                  ri_drdy_1;              // From p1 of port_macro.v
  wire                  ri_drdy_2;              // From p2 of port_macro.v
  wire                  ri_drdy_3;              // From p3 of port_macro.v
  wire                  ri_srdy_0;              // From p3 of port_macro.v
  wire                  ri_srdy_1;              // From p0 of port_macro.v
  wire                  ri_srdy_2;              // From p1 of port_macro.v
  wire                  ri_srdy_3;              // From p2 of port_macro.v
  // End of automatics
 
  /* port_macro AUTO_TEMPLATE
   (
   .clk                         (clk),
   .reset                       (reset),
   .ri_data                     (ri_data_@),
   .ro_\(.*\)        (ri_\1_@"(% (+ 1 @) 4)"),
   .p2f_srdy                            (p2f_srdy[@]),
   .p2f_drdy                            (p2f_drdy[@]),
   .fli_srdy                            (flo_srdy[@]),
   .fli_drdy                            (flo_drdy[@]),
   .fli_data                            (flo_data),
   .\(.*\)     (\1_@[]),
   );
   */
  port_macro #(0) p0
    (/*AUTOINST*/
     // Outputs
     .ro_data                           (ri_data_1),             // Templated
     .fli_drdy                          (flo_drdy[0]),           // Templated
     .gmii_tx_en                        (gmii_tx_en_0),          // Templated
     .gmii_txd                          (gmii_txd_0[7:0]),       // Templated
     .p2f_data                          (p2f_data_0[`PAR_DATA_SZ-1:0]), // Templated
     .p2f_srdy                          (p2f_srdy[0]),           // Templated
     .ri_drdy                           (ri_drdy_0),             // Templated
     .ro_srdy                           (ri_srdy_1),             // Templated
     // Inputs
     .clk                               (clk),                   // Templated
     .reset                             (reset),                 // Templated
     .ri_data                           (ri_data_0),             // Templated
     .fli_data                          (flo_data),              // Templated
     .fli_srdy                          (flo_srdy[0]),           // Templated
     .gmii_rx_clk                       (gmii_rx_clk_0),         // Templated
     .gmii_rx_dv                        (gmii_rx_dv_0),          // Templated
     .gmii_rxd                          (gmii_rxd_0[7:0]),       // Templated
     .p2f_drdy                          (p2f_drdy[0]),           // Templated
     .ri_srdy                           (ri_srdy_0),             // Templated
     .ro_drdy                           (ri_drdy_1));             // Templated
 
  port_macro #(1) p1
    (/*AUTOINST*/
     // Outputs
     .ro_data                           (ri_data_2),             // Templated
     .fli_drdy                          (flo_drdy[1]),           // Templated
     .gmii_tx_en                        (gmii_tx_en_1),          // Templated
     .gmii_txd                          (gmii_txd_1[7:0]),       // Templated
     .p2f_data                          (p2f_data_1[`PAR_DATA_SZ-1:0]), // Templated
     .p2f_srdy                          (p2f_srdy[1]),           // Templated
     .ri_drdy                           (ri_drdy_1),             // Templated
     .ro_srdy                           (ri_srdy_2),             // Templated
     // Inputs
     .clk                               (clk),                   // Templated
     .reset                             (reset),                 // Templated
     .ri_data                           (ri_data_1),             // Templated
     .fli_data                          (flo_data),              // Templated
     .fli_srdy                          (flo_srdy[1]),           // Templated
     .gmii_rx_clk                       (gmii_rx_clk_1),         // Templated
     .gmii_rx_dv                        (gmii_rx_dv_1),          // Templated
     .gmii_rxd                          (gmii_rxd_1[7:0]),       // Templated
     .p2f_drdy                          (p2f_drdy[1]),           // Templated
     .ri_srdy                           (ri_srdy_1),             // Templated
     .ro_drdy                           (ri_drdy_2));             // Templated
 
  port_macro #(2) p2
    (/*AUTOINST*/
     // Outputs
     .ro_data                           (ri_data_3),             // Templated
     .fli_drdy                          (flo_drdy[2]),           // Templated
     .gmii_tx_en                        (gmii_tx_en_2),          // Templated
     .gmii_txd                          (gmii_txd_2[7:0]),       // Templated
     .p2f_data                          (p2f_data_2[`PAR_DATA_SZ-1:0]), // Templated
     .p2f_srdy                          (p2f_srdy[2]),           // Templated
     .ri_drdy                           (ri_drdy_2),             // Templated
     .ro_srdy                           (ri_srdy_3),             // Templated
     // Inputs
     .clk                               (clk),                   // Templated
     .reset                             (reset),                 // Templated
     .ri_data                           (ri_data_2),             // Templated
     .fli_data                          (flo_data),              // Templated
     .fli_srdy                          (flo_srdy[2]),           // Templated
     .gmii_rx_clk                       (gmii_rx_clk_2),         // Templated
     .gmii_rx_dv                        (gmii_rx_dv_2),          // Templated
     .gmii_rxd                          (gmii_rxd_2[7:0]),       // Templated
     .p2f_drdy                          (p2f_drdy[2]),           // Templated
     .ri_srdy                           (ri_srdy_2),             // Templated
     .ro_drdy                           (ri_drdy_3));             // Templated
 
  port_macro #(3) p3
    (/*AUTOINST*/
     // Outputs
     .ro_data                           (ri_data_0),             // Templated
     .fli_drdy                          (flo_drdy[3]),           // Templated
     .gmii_tx_en                        (gmii_tx_en_3),          // Templated
     .gmii_txd                          (gmii_txd_3[7:0]),       // Templated
     .p2f_data                          (p2f_data_3[`PAR_DATA_SZ-1:0]), // Templated
     .p2f_srdy                          (p2f_srdy[3]),           // Templated
     .ri_drdy                           (ri_drdy_3),             // Templated
     .ro_srdy                           (ri_srdy_0),             // Templated
     // Inputs
     .clk                               (clk),                   // Templated
     .reset                             (reset),                 // Templated
     .ri_data                           (ri_data_3),             // Templated
     .fli_data                          (flo_data),              // Templated
     .fli_srdy                          (flo_srdy[3]),           // Templated
     .gmii_rx_clk                       (gmii_rx_clk_3),         // Templated
     .gmii_rx_dv                        (gmii_rx_dv_3),          // Templated
     .gmii_rxd                          (gmii_rxd_3[7:0]),       // Templated
     .p2f_drdy                          (p2f_drdy[3]),           // Templated
     .ri_srdy                           (ri_srdy_3),             // Templated
     .ro_drdy                           (ri_drdy_0));             // Templated
 
/*  sd_rrslow AUTO_TEMPLATE
 (
 .p_data  (ppi_data[`PAR_DATA_SZ-1:0]),
 .c_data  ({p2f_data_3,p2f_data_2,p2f_data_1,p2f_data_0}),
 .c_srdy  (p2f_srdy[`NUM_PORTS-1:0]),
 .c_drdy  (p2f_drdy[`NUM_PORTS-1:0]),
 .c_\(.*\)   (p2f_\1[]),
 .p_\(.*\)   (ppi_\1[]),
 );
 */
  sd_rrslow #(`PAR_DATA_SZ,`NUM_PORTS,0) fib_arb
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (p2f_drdy[`NUM_PORTS-1:0]), // Templated
     .p_data                            (ppi_data[`PAR_DATA_SZ-1:0]), // Templated
     .p_srdy                            (ppi_srdy),              // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_data                            ({p2f_data_3,p2f_data_2,p2f_data_1,p2f_data_0}), // Templated
     .c_srdy                            (p2f_srdy[`NUM_PORTS-1:0]), // Templated
     .p_drdy                            (ppi_drdy));              // Templated
 
  fib_lookup fib_lookup
    (/*AUTOINST*/
     // Outputs
     .flo_data                          (flo_data[`NUM_PORTS-1:0]),
     .flo_srdy                          (flo_srdy[`NUM_PORTS-1:0]),
     .ppi_drdy                          (ppi_drdy),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .ppi_data                          (ppi_data[`PAR_DATA_SZ-1:0]),
     .flo_drdy                          (flo_drdy[`NUM_PORTS-1:0]),
     .ppi_srdy                          (ppi_srdy));
 
endmodule // bridge_ex1
// Local Variables:
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/forks")
// End:  

Line No.	Rev	Author	Line
1	8	ghutchis	`// Top level for bridge example`
2			`//`
3			`// 4-port bridge has 4 GMII interfaces, each one of which has its own RX clock`
4			`// Port macros contain all packet buffering, and ring interface to communicate`
5			`// with other port macros.`
6			`// FIB block receives requests from all ports and sends results back to the`
7			`// same port containing forwarding information.`
8
9			`module bridge_ex1`
10			`(input clk,`
11			`input reset,`
12			`/AUTOINPUT/`
13			`// Beginning of automatic inputs (from unused autoinst inputs)`
14	11	ghutchis	`input gmii_rx_clk_0, // To p0 of port_macro.v`
15			`input gmii_rx_clk_1, // To p1 of port_macro.v`
16			`input gmii_rx_clk_2, // To p2 of port_macro.v`
17			`input gmii_rx_clk_3, // To p3 of port_macro.v`
18			`input gmii_rx_dv_0, // To p0 of port_macro.v`
19			`input gmii_rx_dv_1, // To p1 of port_macro.v`
20			`input gmii_rx_dv_2, // To p2 of port_macro.v`
21			`input gmii_rx_dv_3, // To p3 of port_macro.v`
22			`input [7:0] gmii_rxd_0, // To p0 of port_macro.v`
23			`input [7:0] gmii_rxd_1, // To p1 of port_macro.v`
24			`input [7:0] gmii_rxd_2, // To p2 of port_macro.v`
25			`input [7:0] gmii_rxd_3, // To p3 of port_macro.v`
26	8	ghutchis	`// End of automatics`
27			`/AUTOOUTPUT/`
28			`// Beginning of automatic outputs (from unused autoinst outputs)`
29	11	ghutchis	`output gmii_tx_en_0, // From p0 of port_macro.v`
30			`output gmii_tx_en_1, // From p1 of port_macro.v`
31			`output gmii_tx_en_2, // From p2 of port_macro.v`
32			`output gmii_tx_en_3, // From p3 of port_macro.v`
33			`output [7:0] gmii_txd_0, // From p0 of port_macro.v`
34			`output [7:0] gmii_txd_1, // From p1 of port_macro.v`
35			`output [7:0] gmii_txd_2, // From p2 of port_macro.v`
36			`output [7:0] gmii_txd_3 // From p3 of port_macro.v`
37	8	ghutchis	`// End of automatics`
38			`);`
39
40			wire [`PRW_SZ-1:0] ri_data_0;
41			wire [`PRW_SZ-1:0] ri_data_1;
42			wire [`PRW_SZ-1:0] ri_data_2;
43			wire [`PRW_SZ-1:0] ri_data_3;
44			`/AUTOWIRE/`
45			`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
46	11	ghutchis	wire [`NUM_PORTS-1:0] flo_data; // From fib_lookup of fib_lookup.v
47			`wire [3:0] flo_drdy; // From p0 of port_macro.v, ...`
48			wire [`NUM_PORTS-1:0] flo_srdy; // From fib_lookup of fib_lookup.v
49			wire [`PAR_DATA_SZ-1:0] p2f_data_0; // From p0 of port_macro.v
50			wire [`PAR_DATA_SZ-1:0] p2f_data_1; // From p1 of port_macro.v
51			wire [`PAR_DATA_SZ-1:0] p2f_data_2; // From p2 of port_macro.v
52			wire [`PAR_DATA_SZ-1:0] p2f_data_3; // From p3 of port_macro.v
53			wire [`NUM_PORTS-1:0] p2f_drdy; // From fib_arb of sd_rrslow.v
54			`wire [3:0] p2f_srdy; // From p0 of port_macro.v, ...`
55			wire [`PAR_DATA_SZ-1:0] ppi_data; // From fib_arb of sd_rrslow.v
56			`wire ppi_drdy; // From fib_lookup of fib_lookup.v`
57			`wire ppi_srdy; // From fib_arb of sd_rrslow.v`
58			`wire ri_drdy_0; // From p0 of port_macro.v`
59			`wire ri_drdy_1; // From p1 of port_macro.v`
60			`wire ri_drdy_2; // From p2 of port_macro.v`
61			`wire ri_drdy_3; // From p3 of port_macro.v`
62			`wire ri_srdy_0; // From p3 of port_macro.v`
63			`wire ri_srdy_1; // From p0 of port_macro.v`
64			`wire ri_srdy_2; // From p1 of port_macro.v`
65			`wire ri_srdy_3; // From p2 of port_macro.v`
66	8	ghutchis	`// End of automatics`
67
68			`/* port_macro AUTO_TEMPLATE`
69			`(`
70			`.clk (clk),`
71			`.reset (reset),`
72			`.ri_data (ri_data_@),`
73			`.ro_\(.*\) (ri_\1_@"(% (+ 1 @) 4)"),`
74			`.p2f_srdy (p2f_srdy[@]),`
75			`.p2f_drdy (p2f_drdy[@]),`
76			`.fli_srdy (flo_srdy[@]),`
77			`.fli_drdy (flo_drdy[@]),`
78			`.fli_data (flo_data),`
79			`.\(.*\) (\1_@[]),`
80			`);`
81			`*/`
82	11	ghutchis	`port_macro #(0) p0`
83	8	ghutchis	`(/AUTOINST/`
84			`// Outputs`
85	11	ghutchis	`.ro_data (ri_data_1), // Templated`
86			`.fli_drdy (flo_drdy[0]), // Templated`
87			`.gmii_tx_en (gmii_tx_en_0), // Templated`
88			`.gmii_txd (gmii_txd_0[7:0]), // Templated`
89			.p2f_data (p2f_data_0[`PAR_DATA_SZ-1:0]), // Templated
90			`.p2f_srdy (p2f_srdy[0]), // Templated`
91			`.ri_drdy (ri_drdy_0), // Templated`
92			`.ro_srdy (ri_srdy_1), // Templated`
93	8	ghutchis	`// Inputs`
94	11	ghutchis	`.clk (clk), // Templated`
95			`.reset (reset), // Templated`
96			`.ri_data (ri_data_0), // Templated`
97			`.fli_data (flo_data), // Templated`
98			`.fli_srdy (flo_srdy[0]), // Templated`
99			`.gmii_rx_clk (gmii_rx_clk_0), // Templated`
100			`.gmii_rx_dv (gmii_rx_dv_0), // Templated`
101			`.gmii_rxd (gmii_rxd_0[7:0]), // Templated`
102			`.p2f_drdy (p2f_drdy[0]), // Templated`
103			`.ri_srdy (ri_srdy_0), // Templated`
104			`.ro_drdy (ri_drdy_1)); // Templated`
105	8	ghutchis
106	11	ghutchis	`port_macro #(1) p1`
107	8	ghutchis	`(/AUTOINST/`
108			`// Outputs`
109	11	ghutchis	`.ro_data (ri_data_2), // Templated`
110			`.fli_drdy (flo_drdy[1]), // Templated`
111			`.gmii_tx_en (gmii_tx_en_1), // Templated`
112			`.gmii_txd (gmii_txd_1[7:0]), // Templated`
113			.p2f_data (p2f_data_1[`PAR_DATA_SZ-1:0]), // Templated
114			`.p2f_srdy (p2f_srdy[1]), // Templated`
115			`.ri_drdy (ri_drdy_1), // Templated`
116			`.ro_srdy (ri_srdy_2), // Templated`
117	8	ghutchis	`// Inputs`
118	11	ghutchis	`.clk (clk), // Templated`
119			`.reset (reset), // Templated`
120			`.ri_data (ri_data_1), // Templated`
121			`.fli_data (flo_data), // Templated`
122			`.fli_srdy (flo_srdy[1]), // Templated`
123			`.gmii_rx_clk (gmii_rx_clk_1), // Templated`
124			`.gmii_rx_dv (gmii_rx_dv_1), // Templated`
125			`.gmii_rxd (gmii_rxd_1[7:0]), // Templated`
126			`.p2f_drdy (p2f_drdy[1]), // Templated`
127			`.ri_srdy (ri_srdy_1), // Templated`
128			`.ro_drdy (ri_drdy_2)); // Templated`
129	8	ghutchis
130	11	ghutchis	`port_macro #(2) p2`
131	8	ghutchis	`(/AUTOINST/`
132			`// Outputs`
133	11	ghutchis	`.ro_data (ri_data_3), // Templated`
134			`.fli_drdy (flo_drdy[2]), // Templated`
135			`.gmii_tx_en (gmii_tx_en_2), // Templated`
136			`.gmii_txd (gmii_txd_2[7:0]), // Templated`
137			.p2f_data (p2f_data_2[`PAR_DATA_SZ-1:0]), // Templated
138			`.p2f_srdy (p2f_srdy[2]), // Templated`
139			`.ri_drdy (ri_drdy_2), // Templated`
140			`.ro_srdy (ri_srdy_3), // Templated`
141	8	ghutchis	`// Inputs`
142	11	ghutchis	`.clk (clk), // Templated`
143			`.reset (reset), // Templated`
144			`.ri_data (ri_data_2), // Templated`
145			`.fli_data (flo_data), // Templated`
146			`.fli_srdy (flo_srdy[2]), // Templated`
147			`.gmii_rx_clk (gmii_rx_clk_2), // Templated`
148			`.gmii_rx_dv (gmii_rx_dv_2), // Templated`
149			`.gmii_rxd (gmii_rxd_2[7:0]), // Templated`
150			`.p2f_drdy (p2f_drdy[2]), // Templated`
151			`.ri_srdy (ri_srdy_2), // Templated`
152			`.ro_drdy (ri_drdy_3)); // Templated`
153	8	ghutchis
154	11	ghutchis	`port_macro #(3) p3`
155	8	ghutchis	`(/AUTOINST/`
156			`// Outputs`
157	11	ghutchis	`.ro_data (ri_data_0), // Templated`
158			`.fli_drdy (flo_drdy[3]), // Templated`
159			`.gmii_tx_en (gmii_tx_en_3), // Templated`
160			`.gmii_txd (gmii_txd_3[7:0]), // Templated`
161			.p2f_data (p2f_data_3[`PAR_DATA_SZ-1:0]), // Templated
162			`.p2f_srdy (p2f_srdy[3]), // Templated`
163			`.ri_drdy (ri_drdy_3), // Templated`
164			`.ro_srdy (ri_srdy_0), // Templated`
165	8	ghutchis	`// Inputs`
166	11	ghutchis	`.clk (clk), // Templated`
167			`.reset (reset), // Templated`
168			`.ri_data (ri_data_3), // Templated`
169			`.fli_data (flo_data), // Templated`
170			`.fli_srdy (flo_srdy[3]), // Templated`
171			`.gmii_rx_clk (gmii_rx_clk_3), // Templated`
172			`.gmii_rx_dv (gmii_rx_dv_3), // Templated`
173			`.gmii_rxd (gmii_rxd_3[7:0]), // Templated`
174			`.p2f_drdy (p2f_drdy[3]), // Templated`
175			`.ri_srdy (ri_srdy_3), // Templated`
176			`.ro_drdy (ri_drdy_0)); // Templated`
177	8	ghutchis
178			`/* sd_rrslow AUTO_TEMPLATE`
179			`(`
180			.p_data (ppi_data[`PAR_DATA_SZ-1:0]),
181			`.c_data ({p2f_data_3,p2f_data_2,p2f_data_1,p2f_data_0}),`
182			.c_srdy (p2f_srdy[`NUM_PORTS-1:0]),
183			.c_drdy (p2f_drdy[`NUM_PORTS-1:0]),
184			`.c_\(.*\) (p2f_\1[]),`
185			`.p_\(.*\) (ppi_\1[]),`
186			`);`
187			`*/`
188			sd_rrslow #(`PAR_DATA_SZ,`NUM_PORTS,0) fib_arb
189			`(/AUTOINST/`
190			`// Outputs`
191	11	ghutchis	.c_drdy (p2f_drdy[`NUM_PORTS-1:0]), // Templated
192			.p_data (ppi_data[`PAR_DATA_SZ-1:0]), // Templated
193			`.p_srdy (ppi_srdy), // Templated`
194	8	ghutchis	`// Inputs`
195	11	ghutchis	`.clk (clk),`
196			`.reset (reset),`
197			`.c_data ({p2f_data_3,p2f_data_2,p2f_data_1,p2f_data_0}), // Templated`
198			.c_srdy (p2f_srdy[`NUM_PORTS-1:0]), // Templated
199			`.p_drdy (ppi_drdy)); // Templated`
200	8	ghutchis
201			`fib_lookup fib_lookup`
202			`(/AUTOINST/`
203			`// Outputs`
204	11	ghutchis	.flo_data (flo_data[`NUM_PORTS-1:0]),
205			.flo_srdy (flo_srdy[`NUM_PORTS-1:0]),
206			`.ppi_drdy (ppi_drdy),`
207	8	ghutchis	`// Inputs`
208	11	ghutchis	`.clk (clk),`
209			`.reset (reset),`
210			.ppi_data (ppi_data[`PAR_DATA_SZ-1:0]),
211			.flo_drdy (flo_drdy[`NUM_PORTS-1:0]),
212			`.ppi_srdy (ppi_srdy));`
213	8	ghutchis
214			`endmodule // bridge_ex1`
215			`// Local Variables:`
216			`// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/forks")`
217			`// End:`

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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [bridge_ex1.v] - Blame information for rev 11