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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [concentrator.v] - Blame information for rev 18

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module concentrator
  (input         clk,
   input         reset,
   input [7:0]    c_data,
   input [1:0]   c_code,
   input                 c_srdy,                        // To sdin of sd_input.v
   input                 p_drdy,                        // To sdout of sd_output.v
   output                c_drdy,                        // From sdin of sd_input.v
   output reg [`PFW_SZ-1:0] p_data,                      // From sdout of sd_output.v
   output reg            p_srdy,
   output reg            p_commit,
   output reg            p_abort
   // End of automatics
   );
 
  wire [7:0]     ip_data;                // From sdin of sd_input.v
  wire [1:0]     ip_code;
  reg                   ip_drdy;
  wire                  ip_srdy;                // From sdin of sd_input.v
 
  reg [`PFW_SZ-1:0]      nxt_p_data;
  reg                   nxt_p_srdy;
  reg [2:0]              count, nxt_count;
  reg                   nxt_p_abort, nxt_p_commit;
  wire [1:0]            pkt_code = p_data[`PRW_PCC];
 
  sd_input #(8+2) sdin
    (
     // Outputs
     .c_drdy                            (c_drdy),
     .ip_srdy                           (ip_srdy),
     .ip_data                           ({ip_code,ip_data}),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (c_srdy),
     .c_data                            ({c_code,c_data}),
     .ip_drdy                           (ip_drdy));
 
  always @*
    begin
      nxt_p_data = p_data;
      nxt_p_srdy = p_srdy;
      nxt_p_data = p_data;
      nxt_count = count;
      nxt_p_commit = p_commit;
      nxt_p_abort  = 0;
 
      if (p_srdy)
        begin
          if (p_drdy)
            begin
              nxt_p_srdy = 0;
              nxt_p_commit = 0;
              ip_drdy = 1;
              nxt_p_data[`PRW_PCC] = `PCC_DATA;
              nxt_count = 0;
 
              if (ip_srdy)
                begin
                  nxt_count = 1;
                  if (ip_code != `PCC_DATA)
                    nxt_p_data[`PRW_PCC] = ip_code;
                  nxt_p_data[63:56] = ip_data;
                end
            end
        end
      else if (ip_srdy)
        begin
          ip_drdy = 1;
          if (ip_code != `PCC_DATA)
            nxt_p_data[`PRW_PCC] = ip_code;
 
          nxt_count = count + 1;
          case (count)
 
            1 : nxt_p_data[55:48] = ip_data;
            2 : nxt_p_data[47:40] = ip_data;
            3 : nxt_p_data[39:32] = ip_data;
            4 : nxt_p_data[31:24] = ip_data;
            5 : nxt_p_data[23:16] = ip_data;
            6 : nxt_p_data[15: 8] = ip_data;
            7 : nxt_p_data[ 7: 0] = ip_data;
          endcase // case (count)
          if ((count == 7) | (ip_code == `PCC_BADEOP) | (ip_code == `PCC_EOP))
            begin
              if (ip_code == `PCC_EOP)
                begin
                  nxt_p_commit = 1;
                  nxt_p_srdy   = 1;
                  nxt_p_data[`PRW_VALID] = count + 1;
                end
              else if ((ip_code == `PCC_BADEOP) || (pkt_code == `PCC_BADEOP))
                begin
                  nxt_p_abort = 1;
                end
              else
                begin
                  nxt_p_srdy = 1;
                  nxt_p_data[`PRW_VALID] = 0;
                end
            end
        end
    end // always @ *
 
  always @(posedge clk)
    begin
      if (reset)
        begin
          /*AUTORESET*/
          // Beginning of autoreset for uninitialized flops
          count <= 3'h0;
          p_abort <= 1'h0;
          p_commit <= 1'h0;
          p_data <= {(1+(`PFW_SZ-1)){1'b0}};
          p_srdy <= 1'h0;
          // End of automatics
        end
      else
        begin
          p_commit <= #1 nxt_p_commit;
          p_abort  <= #1 nxt_p_abort;
          p_srdy   <= #1 nxt_p_srdy;
          p_data   <= #1 nxt_p_data;
          count    <= #1 nxt_count;
        end // else: !if(reset)
    end
 
endmodule // template_1i1o

Line No.	Rev	Author	Line
1	8	ghutchis	`module concentrator`
2			`(input clk,`
3			`input reset,`
4			`input [7:0] c_data,`
5			`input [1:0] c_code,`
6			`input c_srdy, // To sdin of sd_input.v`
7			`input p_drdy, // To sdout of sd_output.v`
8			`output c_drdy, // From sdin of sd_input.v`
9			output reg [`PFW_SZ-1:0] p_data, // From sdout of sd_output.v
10			`output reg p_srdy,`
11			`output reg p_commit,`
12			`output reg p_abort`
13			`// End of automatics`
14			`);`
15
16			`wire [7:0] ip_data; // From sdin of sd_input.v`
17			`wire [1:0] ip_code;`
18			`reg ip_drdy;`
19			`wire ip_srdy; // From sdin of sd_input.v`
20
21			reg [`PFW_SZ-1:0] nxt_p_data;
22			`reg nxt_p_srdy;`
23			`reg [2:0] count, nxt_count;`
24			`reg nxt_p_abort, nxt_p_commit;`
25	11	ghutchis	wire [1:0] pkt_code = p_data[`PRW_PCC];
26	8	ghutchis
27			`sd_input #(8+2) sdin`
28			`(`
29			`// Outputs`
30			`.c_drdy (c_drdy),`
31			`.ip_srdy (ip_srdy),`
32			`.ip_data ({ip_code,ip_data}),`
33			`// Inputs`
34			`.clk (clk),`
35			`.reset (reset),`
36			`.c_srdy (c_srdy),`
37			`.c_data ({c_code,c_data}),`
38			`.ip_drdy (ip_drdy));`
39
40			`always @*`
41			`begin`
42			`nxt_p_data = p_data;`
43			`nxt_p_srdy = p_srdy;`
44			`nxt_p_data = p_data;`
45			`nxt_count = count;`
46			`nxt_p_commit = p_commit;`
47			`nxt_p_abort = 0;`
48
49			`if (p_srdy)`
50			`begin`
51			`if (p_drdy)`
52			`begin`
53			`nxt_p_srdy = 0;`
54	9	ghutchis	`nxt_p_commit = 0;`
55	8	ghutchis	`ip_drdy = 1;`
56	11	ghutchis	nxt_p_data[`PRW_PCC] = `PCC_DATA;
57	8	ghutchis	`nxt_count = 0;`
58
59			`if (ip_srdy)`
60			`begin`
61			`nxt_count = 1;`
62			if (ip_code != `PCC_DATA)
63	11	ghutchis	nxt_p_data[`PRW_PCC] = ip_code;
64	8	ghutchis	`nxt_p_data[63:56] = ip_data;`
65			`end`
66			`end`
67			`end`
68			`else if (ip_srdy)`
69			`begin`
70			`ip_drdy = 1;`
71			if (ip_code != `PCC_DATA)
72	11	ghutchis	nxt_p_data[`PRW_PCC] = ip_code;
73	8	ghutchis
74			`nxt_count = count + 1;`
75			`case (count)`
76
77			`1 : nxt_p_data[55:48] = ip_data;`
78			`2 : nxt_p_data[47:40] = ip_data;`
79			`3 : nxt_p_data[39:32] = ip_data;`
80			`4 : nxt_p_data[31:24] = ip_data;`
81			`5 : nxt_p_data[23:16] = ip_data;`
82			`6 : nxt_p_data[15: 8] = ip_data;`
83			`7 : nxt_p_data[ 7: 0] = ip_data;`
84			`endcase // case (count)`
85			if ((count == 7) \| (ip_code == `PCC_BADEOP) \| (ip_code == `PCC_EOP))
86			`begin`
87	9	ghutchis	if (ip_code == `PCC_EOP)
88	8	ghutchis	`begin`
89	9	ghutchis	`nxt_p_commit = 1;`
90			`nxt_p_srdy = 1;`
91	11	ghutchis	nxt_p_data[`PRW_VALID] = count + 1;
92	9	ghutchis	`end`
93			else if ((ip_code == `PCC_BADEOP) \|\| (pkt_code == `PCC_BADEOP))
94			`begin`
95	8	ghutchis	`nxt_p_abort = 1;`
96			`end`
97			`else`
98	11	ghutchis	`begin`
99			`nxt_p_srdy = 1;`
100			nxt_p_data[`PRW_VALID] = 0;
101			`end`
102	8	ghutchis	`end`
103			`end`
104			`end // always @ *`
105
106			`always @(posedge clk)`
107			`begin`
108			`if (reset)`
109			`begin`
110			`/AUTORESET/`
111			`// Beginning of autoreset for uninitialized flops`
112	9	ghutchis	`count <= 3'h0;`
113	8	ghutchis	`p_abort <= 1'h0;`
114			`p_commit <= 1'h0;`
115			p_data <= {(1+(`PFW_SZ-1)){1'b0}};
116			`p_srdy <= 1'h0;`
117			`// End of automatics`
118			`end`
119			`else`
120			`begin`
121			`p_commit <= #1 nxt_p_commit;`
122			`p_abort <= #1 nxt_p_abort;`
123			`p_srdy <= #1 nxt_p_srdy;`
124			`p_data <= #1 nxt_p_data;`
125	9	ghutchis	`count <= #1 nxt_count;`
126	8	ghutchis	`end // else: !if(reset)`
127			`end`
128
129			`endmodule // template_1i1o`

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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [concentrator.v] - Blame information for rev 18