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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [concentrator.v] - Blame information for rev 8

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module concentrator
  (input         clk,
   input         reset,
   input [7:0]    c_data,
   input [1:0]   c_code,
   input                 c_srdy,                        // To sdin of sd_input.v
   input                 p_drdy,                        // To sdout of sd_output.v
   output                c_drdy,                        // From sdin of sd_input.v
   output reg [`PFW_SZ-1:0] p_data,                      // From sdout of sd_output.v
   output reg            p_srdy,
   output reg            p_commit,
   output reg            p_abort
   // End of automatics
   );
 
  wire [`PFW_SZ-1:0]     ic_data;                // From body of template_body_1i1o.v
  wire                  ic_drdy;                // From sdout of sd_output.v
  wire                  ic_srdy;                // From body of template_body_1i1o.v
  wire [7:0]     ip_data;                // From sdin of sd_input.v
  wire [1:0]     ip_code;
  reg                   ip_drdy;
  wire                  ip_srdy;                // From sdin of sd_input.v
 
  reg [`PFW_SZ-1:0]      nxt_p_data;
  reg [1:0]              nxt_pkt_code, pkt_code;
  reg                   nxt_p_srdy;
  reg [2:0]              count, nxt_count;
  reg                   nxt_p_abort, nxt_p_commit;
 
  sd_input #(8+2) sdin
    (
     // Outputs
     .c_drdy                            (c_drdy),
     .ip_srdy                           (ip_srdy),
     .ip_data                           ({ip_code,ip_data}),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (c_srdy),
     .c_data                            ({c_code,c_data}),
     .ip_drdy                           (ip_drdy));
 
  always @*
    begin
      nxt_p_data = p_data;
      nxt_p_srdy = p_srdy;
      nxt_pkt_code = pkt_code;
      nxt_p_data = p_data;
      nxt_count = count;
      nxt_p_commit = p_commit;
      nxt_p_abort  = 0;
 
      if (p_srdy)
        begin
          if (p_drdy)
            begin
              nxt_p_srdy = 0;
              ip_drdy = 1;
              nxt_pkt_code = `PCC_DATA;
              nxt_count = 0;
 
              if (ip_srdy)
                begin
                  nxt_count = 1;
                  if (ip_code != `PCC_DATA)
                    nxt_pkt_code = ip_code;
                  nxt_p_data[63:56] = ip_data;
                end
            end
        end
      else if (ip_srdy)
        begin
          ip_drdy = 1;
          if (ip_code != `PCC_DATA)
            nxt_pkt_code = ip_code;
 
          nxt_count = count + 1;
          case (count)
 
            1 : nxt_p_data[55:48] = ip_data;
            2 : nxt_p_data[47:40] = ip_data;
            3 : nxt_p_data[39:32] = ip_data;
            4 : nxt_p_data[31:24] = ip_data;
            5 : nxt_p_data[23:16] = ip_data;
            6 : nxt_p_data[15: 8] = ip_data;
            7 : nxt_p_data[ 7: 0] = ip_data;
          endcase // case (count)
          if ((count == 7) | (ip_code == `PCC_BADEOP) | (ip_code == `PCC_EOP))
            begin
              if ((ip_code == `PCC_BADEOP) || (pkt_code == `PCC_BADEOP))
                begin
                  nxt_p_abort = 1;
                end
              else
                nxt_p_srdy = 1;
            end
        end
    end // always @ *
 
  always @(posedge clk)
    begin
      if (reset)
        begin
          /*AUTORESET*/
          // Beginning of autoreset for uninitialized flops
          p_abort <= 1'h0;
          p_commit <= 1'h0;
          p_data <= {(1+(`PFW_SZ-1)){1'b0}};
          p_srdy <= 1'h0;
          // End of automatics
        end
      else
        begin
          p_commit <= #1 nxt_p_commit;
          p_abort  <= #1 nxt_p_abort;
          p_srdy   <= #1 nxt_p_srdy;
          p_data   <= #1 nxt_p_data;
        end // else: !if(reset)
    end
 
endmodule // template_1i1o

Line No.	Rev	Author	Line
1	8	ghutchis	`module concentrator`
2			`(input clk,`
3			`input reset,`
4			`input [7:0] c_data,`
5			`input [1:0] c_code,`
6			`input c_srdy, // To sdin of sd_input.v`
7			`input p_drdy, // To sdout of sd_output.v`
8			`output c_drdy, // From sdin of sd_input.v`
9			output reg [`PFW_SZ-1:0] p_data, // From sdout of sd_output.v
10			`output reg p_srdy,`
11			`output reg p_commit,`
12			`output reg p_abort`
13			`// End of automatics`
14			`);`
15
16			wire [`PFW_SZ-1:0] ic_data; // From body of template_body_1i1o.v
17			`wire ic_drdy; // From sdout of sd_output.v`
18			`wire ic_srdy; // From body of template_body_1i1o.v`
19			`wire [7:0] ip_data; // From sdin of sd_input.v`
20			`wire [1:0] ip_code;`
21			`reg ip_drdy;`
22			`wire ip_srdy; // From sdin of sd_input.v`
23
24			reg [`PFW_SZ-1:0] nxt_p_data;
25			`reg [1:0] nxt_pkt_code, pkt_code;`
26			`reg nxt_p_srdy;`
27			`reg [2:0] count, nxt_count;`
28			`reg nxt_p_abort, nxt_p_commit;`
29
30			`sd_input #(8+2) sdin`
31			`(`
32			`// Outputs`
33			`.c_drdy (c_drdy),`
34			`.ip_srdy (ip_srdy),`
35			`.ip_data ({ip_code,ip_data}),`
36			`// Inputs`
37			`.clk (clk),`
38			`.reset (reset),`
39			`.c_srdy (c_srdy),`
40			`.c_data ({c_code,c_data}),`
41			`.ip_drdy (ip_drdy));`
42
43			`always @*`
44			`begin`
45			`nxt_p_data = p_data;`
46			`nxt_p_srdy = p_srdy;`
47			`nxt_pkt_code = pkt_code;`
48			`nxt_p_data = p_data;`
49			`nxt_count = count;`
50			`nxt_p_commit = p_commit;`
51			`nxt_p_abort = 0;`
52
53			`if (p_srdy)`
54			`begin`
55			`if (p_drdy)`
56			`begin`
57			`nxt_p_srdy = 0;`
58			`ip_drdy = 1;`
59			nxt_pkt_code = `PCC_DATA;
60			`nxt_count = 0;`
61
62			`if (ip_srdy)`
63			`begin`
64			`nxt_count = 1;`
65			if (ip_code != `PCC_DATA)
66			`nxt_pkt_code = ip_code;`
67			`nxt_p_data[63:56] = ip_data;`
68			`end`
69			`end`
70			`end`
71			`else if (ip_srdy)`
72			`begin`
73			`ip_drdy = 1;`
74			if (ip_code != `PCC_DATA)
75			`nxt_pkt_code = ip_code;`
76
77			`nxt_count = count + 1;`
78			`case (count)`
79
80			`1 : nxt_p_data[55:48] = ip_data;`
81			`2 : nxt_p_data[47:40] = ip_data;`
82			`3 : nxt_p_data[39:32] = ip_data;`
83			`4 : nxt_p_data[31:24] = ip_data;`
84			`5 : nxt_p_data[23:16] = ip_data;`
85			`6 : nxt_p_data[15: 8] = ip_data;`
86			`7 : nxt_p_data[ 7: 0] = ip_data;`
87			`endcase // case (count)`
88			if ((count == 7) \| (ip_code == `PCC_BADEOP) \| (ip_code == `PCC_EOP))
89			`begin`
90			if ((ip_code == `PCC_BADEOP) \|\| (pkt_code == `PCC_BADEOP))
91			`begin`
92			`nxt_p_abort = 1;`
93			`end`
94			`else`
95			`nxt_p_srdy = 1;`
96			`end`
97			`end`
98			`end // always @ *`
99
100			`always @(posedge clk)`
101			`begin`
102			`if (reset)`
103			`begin`
104			`/AUTORESET/`
105			`// Beginning of autoreset for uninitialized flops`
106			`p_abort <= 1'h0;`
107			`p_commit <= 1'h0;`
108			p_data <= {(1+(`PFW_SZ-1)){1'b0}};
109			`p_srdy <= 1'h0;`
110			`// End of automatics`
111			`end`
112			`else`
113			`begin`
114			`p_commit <= #1 nxt_p_commit;`
115			`p_abort <= #1 nxt_p_abort;`
116			`p_srdy <= #1 nxt_p_srdy;`
117			`p_data <= #1 nxt_p_data;`
118			`end // else: !if(reset)`
119			`end`
120
121			`endmodule // template_1i1o`

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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [concentrator.v] - Blame information for rev 8