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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [distributor.v] - Blame information for rev 11

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1 8 ghutchis
module distributor
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  (input         clk,
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   input         reset,
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   input         ptx_srdy,
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   output        ptx_drdy,
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   input [`PFW_SZ-1:0] ptx_data,
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   output        p_srdy,
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   input         p_drdy,
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   output [1:0]  p_code,
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   output [7:0]  p_data
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   );
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15 11 ghutchis
  reg [7:0]      ic_data;
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  reg [1:0]     ic_code;
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  wire          ic_drdy;
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  reg           ic_srdy;
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  wire [`PFW_SZ-1:0] ip_data;
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  reg                ip_drdy;
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  wire               ip_srdy;
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  reg [7:0]          remain, nxt_remain;
23 8 ghutchis
 
24 11 ghutchis
  sd_input #(`PFW_SZ) sdin
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    (
26 8 ghutchis
     // Outputs
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     .c_drdy                            (ptx_drdy),
28 8 ghutchis
     .ip_srdy                           (ip_srdy),
29 11 ghutchis
     .ip_data                           (ip_data),
30 8 ghutchis
     // Inputs
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     .clk                               (clk),
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     .reset                             (reset),
33 11 ghutchis
     .c_srdy                            (ptx_srdy),
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     .c_data                            (ptx_data),
35 8 ghutchis
     .ip_drdy                           (ip_drdy));
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37 11 ghutchis
  always @*
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    begin
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      nxt_remain = remain;
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      ic_srdy = 0;
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      ip_drdy = 0;
42 8 ghutchis
 
43 11 ghutchis
      case (remain)
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        7 : ic_data = ip_data[55:48];
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        6 : ic_data = ip_data[47:40];
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        5 : ic_data = ip_data[39:32];
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        4 : ic_data = ip_data[31:24];
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        3 : ic_data = ip_data[23:16];
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        2 : ic_data = ip_data[15: 8];
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        1 : ic_data = ip_data[ 7: 0];
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        default : ic_data = ip_data[63:56];
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      endcase
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      if (ip_srdy & ic_drdy)
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        begin
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          if (remain == 0)
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            begin
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              ic_srdy = 1;
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              if (ip_data[`PRW_VALID] == 0)
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                nxt_remain = 7;
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              else
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                nxt_remain = ip_data[`PRW_VALID]-1;
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              if (nxt_remain == 0)
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                ip_drdy = 1;
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              if (ip_data[`PRW_PCC] == `PCC_SOP)
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                ic_code = `PCC_SOP;
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              else
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                ic_code = `PCC_DATA;
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            end // if (remain == 0)
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          else
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            begin
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              ic_srdy = 1;
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              nxt_remain = remain - 1;
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              if (nxt_remain == 0)
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                begin
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                  ip_drdy = 1;
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                  if ((ip_data[`PRW_PCC] == `PCC_EOP) |
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                      (ip_data[`PRW_PCC] == `PCC_BADEOP))
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                    ic_code = ip_data[`PRW_PCC];
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                  else
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                    ic_code = `PCC_DATA;
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                end
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              else
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                ic_code = `PCC_DATA;
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            end // else: !if(remain == 0)
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        end
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    end // always @ *
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  always @(posedge clk)
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    begin
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      if (reset)
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        remain <= #1 0;
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      else
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        remain <= #1 nxt_remain;
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    end
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  sd_output #(8+2) sdout
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    (
102 8 ghutchis
     // Outputs
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     .ic_drdy                           (ic_drdy),
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     .p_srdy                            (p_srdy),
105 11 ghutchis
     .p_data                            ({p_code,p_data}),
106 8 ghutchis
     // Inputs
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     .clk                               (clk),
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     .reset                             (reset),
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     .ic_srdy                           (ic_srdy),
110 11 ghutchis
     .ic_data                           ({ic_code,ic_data}),
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     .p_drdy                            (p_drdy));
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endmodule // template_1i1o
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// Local Variables:
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// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
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// End:  

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