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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [distributor.v] - Blame information for rev 18

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module distributor
  (input         clk,
   input         reset,
 
   input         ptx_srdy,
   output        ptx_drdy,
   input [`PFW_SZ-1:0] ptx_data,
 
   output        p_srdy,
   input         p_drdy,
   output [1:0]  p_code,
   output [7:0]  p_data
   );
 
  reg [7:0]      ic_data;
  reg [1:0]     ic_code;
  wire          ic_drdy;
  reg           ic_srdy;
  wire [`PFW_SZ-1:0] ip_data;
  reg                ip_drdy;
  wire               ip_srdy;
  reg [7:0]          remain, nxt_remain;
 
  sd_input #(`PFW_SZ) sdin
    (
     // Outputs
     .c_drdy                            (ptx_drdy),
     .ip_srdy                           (ip_srdy),
     .ip_data                           (ip_data),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (ptx_srdy),
     .c_data                            (ptx_data),
     .ip_drdy                           (ip_drdy));
 
  always @*
    begin
      nxt_remain = remain;
      ic_srdy = 0;
      ip_drdy = 0;
 
      case (remain)
 
        7 : ic_data = ip_data[55:48];
        6 : ic_data = ip_data[47:40];
        5 : ic_data = ip_data[39:32];
        4 : ic_data = ip_data[31:24];
        3 : ic_data = ip_data[23:16];
        2 : ic_data = ip_data[15: 8];
        1 : ic_data = ip_data[ 7: 0];
        default : ic_data = ip_data[63:56];
      endcase
 
      if (ip_srdy & ic_drdy)
        begin
          if (remain == 0)
            begin
              ic_srdy = 1;
              if (ip_data[`PRW_VALID] == 0)
                nxt_remain = 7;
              else
                nxt_remain = ip_data[`PRW_VALID]-1;
 
              if (nxt_remain == 0)
                ip_drdy = 1;
 
              if (ip_data[`PRW_PCC] == `PCC_SOP)
                ic_code = `PCC_SOP;
              else
                ic_code = `PCC_DATA;
            end // if (remain == 0)
          else
            begin
              ic_srdy = 1;
              nxt_remain = remain - 1;
              if (nxt_remain == 0)
                begin
                  ip_drdy = 1;
                  if ((ip_data[`PRW_PCC] == `PCC_EOP) |
                      (ip_data[`PRW_PCC] == `PCC_BADEOP))
                    ic_code = ip_data[`PRW_PCC];
                  else
                    ic_code = `PCC_DATA;
                end
              else
                ic_code = `PCC_DATA;
            end // else: !if(remain == 0)
        end
    end // always @ *
 
  always @(posedge clk)
    begin
      if (reset)
        remain <= #1 0;
      else
        remain <= #1 nxt_remain;
    end
 
  sd_output #(8+2) sdout
    (
     // Outputs
     .ic_drdy                           (ic_drdy),
     .p_srdy                            (p_srdy),
     .p_data                            ({p_code,p_data}),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .ic_srdy                           (ic_srdy),
     .ic_data                           ({ic_code,ic_data}),
     .p_drdy                            (p_drdy));
 
endmodule // template_1i1o
 
// Local Variables:
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
// End:  

Line No.	Rev	Author	Line
1	8	ghutchis	`module distributor`
2			`(input clk,`
3			`input reset,`
4
5			`input ptx_srdy,`
6			`output ptx_drdy,`
7			input [`PFW_SZ-1:0] ptx_data,
8
9			`output p_srdy,`
10			`input p_drdy,`
11			`output [1:0] p_code,`
12			`output [7:0] p_data`
13			`);`
14
15	11	ghutchis	`reg [7:0] ic_data;`
16			`reg [1:0] ic_code;`
17			`wire ic_drdy;`
18			`reg ic_srdy;`
19			wire [`PFW_SZ-1:0] ip_data;
20			`reg ip_drdy;`
21			`wire ip_srdy;`
22			`reg [7:0] remain, nxt_remain;`
23	8	ghutchis
24	11	ghutchis	sd_input #(`PFW_SZ) sdin
25			`(`
26	8	ghutchis	`// Outputs`
27	11	ghutchis	`.c_drdy (ptx_drdy),`
28	8	ghutchis	`.ip_srdy (ip_srdy),`
29	11	ghutchis	`.ip_data (ip_data),`
30	8	ghutchis	`// Inputs`
31			`.clk (clk),`
32			`.reset (reset),`
33	11	ghutchis	`.c_srdy (ptx_srdy),`
34			`.c_data (ptx_data),`
35	8	ghutchis	`.ip_drdy (ip_drdy));`
36
37	11	ghutchis	`always @*`
38			`begin`
39			`nxt_remain = remain;`
40			`ic_srdy = 0;`
41			`ip_drdy = 0;`
42	8	ghutchis
43	11	ghutchis	`case (remain)`
44
45			`7 : ic_data = ip_data[55:48];`
46			`6 : ic_data = ip_data[47:40];`
47			`5 : ic_data = ip_data[39:32];`
48			`4 : ic_data = ip_data[31:24];`
49			`3 : ic_data = ip_data[23:16];`
50			`2 : ic_data = ip_data[15: 8];`
51			`1 : ic_data = ip_data[ 7: 0];`
52			`default : ic_data = ip_data[63:56];`
53			`endcase`
54
55			`if (ip_srdy & ic_drdy)`
56			`begin`
57			`if (remain == 0)`
58			`begin`
59			`ic_srdy = 1;`
60			if (ip_data[`PRW_VALID] == 0)
61			`nxt_remain = 7;`
62			`else`
63			nxt_remain = ip_data[`PRW_VALID]-1;
64
65			`if (nxt_remain == 0)`
66			`ip_drdy = 1;`
67
68			if (ip_data[`PRW_PCC] == `PCC_SOP)
69			ic_code = `PCC_SOP;
70			`else`
71			ic_code = `PCC_DATA;
72			`end // if (remain == 0)`
73			`else`
74			`begin`
75			`ic_srdy = 1;`
76			`nxt_remain = remain - 1;`
77			`if (nxt_remain == 0)`
78			`begin`
79			`ip_drdy = 1;`
80			if ((ip_data[`PRW_PCC] == `PCC_EOP) \|
81			(ip_data[`PRW_PCC] == `PCC_BADEOP))
82			ic_code = ip_data[`PRW_PCC];
83			`else`
84			ic_code = `PCC_DATA;
85			`end`
86			`else`
87			ic_code = `PCC_DATA;
88			`end // else: !if(remain == 0)`
89			`end`
90			`end // always @ *`
91
92			`always @(posedge clk)`
93			`begin`
94			`if (reset)`
95			`remain <= #1 0;`
96			`else`
97			`remain <= #1 nxt_remain;`
98			`end`
99
100			`sd_output #(8+2) sdout`
101			`(`
102	8	ghutchis	`// Outputs`
103			`.ic_drdy (ic_drdy),`
104			`.p_srdy (p_srdy),`
105	11	ghutchis	`.p_data ({p_code,p_data}),`
106	8	ghutchis	`// Inputs`
107			`.clk (clk),`
108			`.reset (reset),`
109			`.ic_srdy (ic_srdy),`
110	11	ghutchis	`.ic_data ({ic_code,ic_data}),`
111	8	ghutchis	`.p_drdy (p_drdy));`
112
113			`endmodule // template_1i1o`
114
115			`// Local Variables:`
116			`// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")`
117			`// End:`

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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [distributor.v] - Blame information for rev 18