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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [distributor.v] - Blame information for rev 8

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module distributor
  #(parameter width=8)
  (input         clk,
   input         reset,
 
   input         ptx_srdy,
   output        ptx_drdy,
   input [`PFW_SZ-1:0] ptx_data,
 
   output        p_srdy,
   input         p_drdy,
   output [1:0]  p_code,
   output [7:0]  p_data
   );
 
  wire [width-1:0]       ic_data;                // From body of template_body_1i1o.v
  wire                  ic_drdy;                // From sdout of sd_output.v
  wire                  ic_srdy;                // From body of template_body_1i1o.v
  wire [width-1:0]       ip_data;                // From sdin of sd_input.v
  wire                  ip_drdy;                // From body of template_body_1i1o.v
  wire                  ip_srdy;                // From sdin of sd_input.v
  // End of automatics
 
  sd_input #(width) sdin
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (c_drdy),
     .ip_srdy                           (ip_srdy),
     .ip_data                           (ip_data[width-1:0]),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (c_srdy),
     .c_data                            (c_data[width-1:0]),
     .ip_drdy                           (ip_drdy));
 
  template_body_1i1o #(width) body
    (/*AUTOINST*/
     // Outputs
     .ic_data                           (ic_data[width-1:0]),
     .ic_srdy                           (ic_srdy),
     .ip_drdy                           (ip_drdy),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .ic_drdy                           (ic_drdy),
     .ip_data                           (ip_data[width-1:0]),
     .ip_srdy                           (ip_srdy));
 
  sd_output #(width) sdout
    (/*AUTOINST*/
     // Outputs
     .ic_drdy                           (ic_drdy),
     .p_srdy                            (p_srdy),
     .p_data                            (p_data[width-1:0]),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .ic_srdy                           (ic_srdy),
     .ic_data                           (ic_data[width-1:0]),
     .p_drdy                            (p_drdy));
 
endmodule // template_1i1o
 
module template_body_1i1o
  #(parameter width=8)
  (input                  clk,
   input                  reset,
   output reg [width-1:0] ic_data,
   output reg             ic_srdy,
   output reg             ip_drdy,
   input                  ic_drdy,
   input [width-1:0]       ip_data,
   input                  ip_srdy
   );
 
   always @*
     begin
       ic_data = ip_data;
       if (ip_srdy & ip_drdy)
         begin
           ic_srdy = 1;
           ip_drdy = 1;
         end
       else
         begin
           ic_srdy = 0;
           ip_drdy = 0;
         end
     end
 
endmodule // template_body_1i1o
 
// Local Variables:
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
// End:  

Line No.	Rev	Author	Line
1	8	ghutchis	`module distributor`
2			`#(parameter width=8)`
3			`(input clk,`
4			`input reset,`
5
6			`input ptx_srdy,`
7			`output ptx_drdy,`
8			input [`PFW_SZ-1:0] ptx_data,
9
10			`output p_srdy,`
11			`input p_drdy,`
12			`output [1:0] p_code,`
13			`output [7:0] p_data`
14			`);`
15
16			`wire [width-1:0] ic_data; // From body of template_body_1i1o.v`
17			`wire ic_drdy; // From sdout of sd_output.v`
18			`wire ic_srdy; // From body of template_body_1i1o.v`
19			`wire [width-1:0] ip_data; // From sdin of sd_input.v`
20			`wire ip_drdy; // From body of template_body_1i1o.v`
21			`wire ip_srdy; // From sdin of sd_input.v`
22			`// End of automatics`
23
24			`sd_input #(width) sdin`
25			`(/AUTOINST/`
26			`// Outputs`
27			`.c_drdy (c_drdy),`
28			`.ip_srdy (ip_srdy),`
29			`.ip_data (ip_data[width-1:0]),`
30			`// Inputs`
31			`.clk (clk),`
32			`.reset (reset),`
33			`.c_srdy (c_srdy),`
34			`.c_data (c_data[width-1:0]),`
35			`.ip_drdy (ip_drdy));`
36
37			`template_body_1i1o #(width) body`
38			`(/AUTOINST/`
39			`// Outputs`
40			`.ic_data (ic_data[width-1:0]),`
41			`.ic_srdy (ic_srdy),`
42			`.ip_drdy (ip_drdy),`
43			`// Inputs`
44			`.clk (clk),`
45			`.reset (reset),`
46			`.ic_drdy (ic_drdy),`
47			`.ip_data (ip_data[width-1:0]),`
48			`.ip_srdy (ip_srdy));`
49
50			`sd_output #(width) sdout`
51			`(/AUTOINST/`
52			`// Outputs`
53			`.ic_drdy (ic_drdy),`
54			`.p_srdy (p_srdy),`
55			`.p_data (p_data[width-1:0]),`
56			`// Inputs`
57			`.clk (clk),`
58			`.reset (reset),`
59			`.ic_srdy (ic_srdy),`
60			`.ic_data (ic_data[width-1:0]),`
61			`.p_drdy (p_drdy));`
62
63			`endmodule // template_1i1o`
64
65			`module template_body_1i1o`
66			`#(parameter width=8)`
67			`(input clk,`
68			`input reset,`
69			`output reg [width-1:0] ic_data,`
70			`output reg ic_srdy,`
71			`output reg ip_drdy,`
72			`input ic_drdy,`
73			`input [width-1:0] ip_data,`
74			`input ip_srdy`
75			`);`
76
77			`always @*`
78			`begin`
79			`ic_data = ip_data;`
80			`if (ip_srdy & ip_drdy)`
81			`begin`
82			`ic_srdy = 1;`
83			`ip_drdy = 1;`
84			`end`
85			`else`
86			`begin`
87			`ic_srdy = 0;`
88			`ip_drdy = 0;`
89			`end`
90			`end`
91
92			`endmodule // template_body_1i1o`
93
94			`// Local Variables:`
95			`// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")`
96			`// End:`

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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [distributor.v] - Blame information for rev 8