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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [fib_lookup.v] - Blame information for rev 11

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1 4 ghutchis
// Inputs are PPI (port parser input)
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// Outputs are FLO (FIB lookup out)
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module fib_lookup
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  (/*AUTOARG*/
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  // Outputs
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  ppi_drdy, flo_data, flo_srdy,
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  // Inputs
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  ppi_srdy, clk, reset, ppi_data, flo_drdy
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  );
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  input     clk;
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  input     reset;
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  input [`PAR_DATA_SZ-1:0] ppi_data;
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  output [`NUM_PORTS-1:0]  flo_data;
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  output [`NUM_PORTS-1:0]  flo_srdy;
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  input [`NUM_PORTS-1:0]   flo_drdy;
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  /*AUTOINPUT*/
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  // Beginning of automatic inputs (from unused autoinst inputs)
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  input                 ppi_srdy;               // To port_parse_in of sd_input.v
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  // End of automatics
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  /*AUTOOUTPUT*/
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  // Beginning of automatic outputs (from unused autoinst outputs)
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  output                ppi_drdy;               // From port_parse_in of sd_input.v
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  // End of automatics
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  wire [`FIB_ENTRY_SZ-1:0] ft_rdata;
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  wire [`PAR_DATA_SZ-1:0] lpp_data;
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  /*AUTOWIRE*/
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  // Beginning of automatic wires (for undeclared instantiated-module outputs)
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  wire [`FIB_ASZ-1:0]   ft_addr;                // From fsm0 of fib_lookup_fsm.v
33 5 ghutchis
  wire                  ft_rd_en;               // From fsm0 of fib_lookup_fsm.v
34 4 ghutchis
  wire [`FIB_ENTRY_SZ-1:0] ft_wdata;            // From fsm0 of fib_lookup_fsm.v
35 5 ghutchis
  wire                  ft_wr_en;               // From fsm0 of fib_lookup_fsm.v
36 4 ghutchis
  wire [`NUM_PORTS-1:0] lout_data;              // From fsm0 of fib_lookup_fsm.v
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  wire                  lout_drdy;              // From fib_res_out of sd_mirror.v
38 5 ghutchis
  wire [`NUM_PORTS-1:0] lout_dst_vld;           // From fsm0 of fib_lookup_fsm.v
39 4 ghutchis
  wire                  lout_srdy;              // From fsm0 of fib_lookup_fsm.v
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  wire                  lpp_drdy;               // From fsm0 of fib_lookup_fsm.v
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  wire                  lpp_srdy;               // From port_parse_in of sd_input.v
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  // End of automatics
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/* sd_input AUTO_TEMPLATE
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 (
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 .c_\(.*\)      (ppi_\1),
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 .ip_\(.*\)     (lpp_\1),
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 );
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 */
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  sd_input #(`PAR_DATA_SZ) port_parse_in
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    (/*AUTOINST*/
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     // Outputs
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     .c_drdy                            (ppi_drdy),              // Templated
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     .ip_srdy                           (lpp_srdy),              // Templated
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     .ip_data                           (lpp_data),              // Templated
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     // Inputs
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     .clk                               (clk),
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     .reset                             (reset),
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     .c_srdy                            (ppi_srdy),              // Templated
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     .c_data                            (ppi_data),              // Templated
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     .ip_drdy                           (lpp_drdy));              // Templated
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/* behave1p_mem AUTO_TEMPLATE
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 (
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   .d_out                             (ft_rdata),
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   .d_in                              (ft_wdata),
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   .clk                               (clk),
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   .\(.*\)     (ft_\1),
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 );
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 */
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  behave1p_mem #(`FIB_ENTRIES, `FIB_ENTRY_SZ) fib_mem
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    (/*AUTOINST*/
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     // Outputs
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     .d_out                             (ft_rdata),              // Templated
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     // Inputs
76 5 ghutchis
     .wr_en                             (ft_wr_en),              // Templated
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     .rd_en                             (ft_rd_en),              // Templated
78 4 ghutchis
     .clk                               (clk),                   // Templated
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     .d_in                              (ft_wdata),              // Templated
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     .addr                              (ft_addr));               // Templated
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  fib_lookup_fsm fsm0
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    (/*AUTOINST*/
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     // Outputs
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     .lpp_drdy                          (lpp_drdy),
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     .ft_wdata                          (ft_wdata[`FIB_ENTRY_SZ-1:0]),
87 5 ghutchis
     .ft_rd_en                          (ft_rd_en),
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     .ft_wr_en                          (ft_wr_en),
89 4 ghutchis
     .ft_addr                           (ft_addr[`FIB_ASZ-1:0]),
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     .lout_data                         (lout_data[`NUM_PORTS-1:0]),
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     .lout_srdy                         (lout_srdy),
92 5 ghutchis
     .lout_dst_vld                      (lout_dst_vld[`NUM_PORTS-1:0]),
93 4 ghutchis
     // Inputs
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     .clk                               (clk),
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     .reset                             (reset),
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     .lpp_data                          (lpp_data[`PAR_DATA_SZ-1:0]),
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     .lpp_srdy                          (lpp_srdy),
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     .ft_rdata                          (ft_rdata[`FIB_ENTRY_SZ-1:0]),
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     .lout_drdy                         (lout_drdy));
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/* sd_mirror AUTO_TEMPLATE
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 (
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 .c_\(.*\)     (lout_\1),
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 .p_\(.*\)     (flo_\1),
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 )
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 */
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  sd_mirror #(`NUM_PORTS, `NUM_PORTS) fib_res_out
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    (/*AUTOINST*/
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     // Outputs
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     .c_drdy                            (lout_drdy),             // Templated
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     .p_srdy                            (flo_srdy),              // Templated
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     .p_data                            (flo_data),              // Templated
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     // Inputs
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     .clk                               (clk),
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     .reset                             (reset),
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     .c_srdy                            (lout_srdy),             // Templated
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     .c_data                            (lout_data),             // Templated
118 5 ghutchis
     .c_dst_vld                         (lout_dst_vld),          // Templated
119 4 ghutchis
     .p_drdy                            (flo_drdy));              // Templated
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endmodule // fib_lookup
122 5 ghutchis
// Local Variables:
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// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
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// End:  

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