URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [fib_lookup.v] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log


// Inputs are PPI (port parser input)
// Outputs are FLO (FIB lookup out)
 
module fib_lookup
  (/*AUTOARG*/
  // Outputs
  ppi_drdy, flo_data, flo_srdy,
  // Inputs
  ppi_srdy, clk, reset, ppi_data, flo_drdy
  );
 
  input     clk;
  input     reset;
 
  input [`PAR_DATA_SZ-1:0] ppi_data;
  output [`NUM_PORTS-1:0]  flo_data;
  output [`NUM_PORTS-1:0]  flo_srdy;
  input [`NUM_PORTS-1:0]   flo_drdy;
  /*AUTOINPUT*/
  // Beginning of automatic inputs (from unused autoinst inputs)
  input                 ppi_srdy;               // To port_parse_in of sd_input.v
  // End of automatics
  /*AUTOOUTPUT*/
  // Beginning of automatic outputs (from unused autoinst outputs)
  output                ppi_drdy;               // From port_parse_in of sd_input.v
  // End of automatics
 
  wire [`FIB_ENTRY_SZ-1:0] ft_rdata;
  wire [`PAR_DATA_SZ-1:0] lpp_data;
  /*AUTOWIRE*/
  // Beginning of automatic wires (for undeclared instantiated-module outputs)
  wire [`FIB_ASZ-1:0]   ft_addr;                // From fsm0 of fib_lookup_fsm.v
  wire                  ft_rd_en;               // From fsm0 of fib_lookup_fsm.v
  wire [`FIB_ENTRY_SZ-1:0] ft_wdata;            // From fsm0 of fib_lookup_fsm.v
  wire                  ft_wr_en;               // From fsm0 of fib_lookup_fsm.v
  wire [`NUM_PORTS-1:0] lout_data;              // From fsm0 of fib_lookup_fsm.v
  wire                  lout_drdy;              // From fib_res_out of sd_mirror.v
  wire [`NUM_PORTS-1:0] lout_dst_vld;           // From fsm0 of fib_lookup_fsm.v
  wire                  lout_srdy;              // From fsm0 of fib_lookup_fsm.v
  wire                  lpp_drdy;               // From fsm0 of fib_lookup_fsm.v
  wire                  lpp_srdy;               // From port_parse_in of sd_input.v
  // End of automatics
 
/* sd_input AUTO_TEMPLATE
 (
 .c_\(.*\)      (ppi_\1),
 .ip_\(.*\)     (lpp_\1),
 );
 */
  sd_input #(`PAR_DATA_SZ) port_parse_in
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (ppi_drdy),              // Templated
     .ip_srdy                           (lpp_srdy),              // Templated
     .ip_data                           (lpp_data),              // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (ppi_srdy),              // Templated
     .c_data                            (ppi_data),              // Templated
     .ip_drdy                           (lpp_drdy));              // Templated
 
/* behave1p_mem AUTO_TEMPLATE
 (
   .d_out                             (ft_rdata),
   .d_in                              (ft_wdata),
   .clk                               (clk),
   .\(.*\)     (ft_\1),
 );
 */
  behave1p_mem #(`FIB_ENTRIES, `FIB_ENTRY_SZ) fib_mem
    (/*AUTOINST*/
     // Outputs
     .d_out                             (ft_rdata),              // Templated
     // Inputs
     .wr_en                             (ft_wr_en),              // Templated
     .rd_en                             (ft_rd_en),              // Templated
     .clk                               (clk),                   // Templated
     .d_in                              (ft_wdata),              // Templated
     .addr                              (ft_addr));               // Templated
 
  fib_lookup_fsm fsm0
    (/*AUTOINST*/
     // Outputs
     .lpp_drdy                          (lpp_drdy),
     .ft_wdata                          (ft_wdata[`FIB_ENTRY_SZ-1:0]),
     .ft_rd_en                          (ft_rd_en),
     .ft_wr_en                          (ft_wr_en),
     .ft_addr                           (ft_addr[`FIB_ASZ-1:0]),
     .lout_data                         (lout_data[`NUM_PORTS-1:0]),
     .lout_srdy                         (lout_srdy),
     .lout_dst_vld                      (lout_dst_vld[`NUM_PORTS-1:0]),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .lpp_data                          (lpp_data[`PAR_DATA_SZ-1:0]),
     .lpp_srdy                          (lpp_srdy),
     .ft_rdata                          (ft_rdata[`FIB_ENTRY_SZ-1:0]),
     .lout_drdy                         (lout_drdy));
 
/* sd_mirror AUTO_TEMPLATE
 (
 .c_\(.*\)     (lout_\1),
 .p_\(.*\)     (flo_\1),
 )
 */
  sd_mirror #(`NUM_PORTS, `NUM_PORTS) fib_res_out
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (lout_drdy),             // Templated
     .p_srdy                            (flo_srdy),              // Templated
     .p_data                            (flo_data),              // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (lout_srdy),             // Templated
     .c_data                            (lout_data),             // Templated
     .c_dst_vld                         (lout_dst_vld),          // Templated
     .p_drdy                            (flo_drdy));              // Templated
 
endmodule // fib_lookup
// Local Variables:
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
// End:  

Line No.	Rev	Author	Line
1	4	ghutchis	`// Inputs are PPI (port parser input)`
2			`// Outputs are FLO (FIB lookup out)`
3
4			`module fib_lookup`
5			`(/AUTOARG/`
6			`// Outputs`
7			`ppi_drdy, flo_data, flo_srdy,`
8			`// Inputs`
9			`ppi_srdy, clk, reset, ppi_data, flo_drdy`
10			`);`
11
12			`input clk;`
13			`input reset;`
14
15			input [`PAR_DATA_SZ-1:0] ppi_data;
16			output [`NUM_PORTS-1:0] flo_data;
17			output [`NUM_PORTS-1:0] flo_srdy;
18			input [`NUM_PORTS-1:0] flo_drdy;
19			`/AUTOINPUT/`
20			`// Beginning of automatic inputs (from unused autoinst inputs)`
21			`input ppi_srdy; // To port_parse_in of sd_input.v`
22			`// End of automatics`
23			`/AUTOOUTPUT/`
24			`// Beginning of automatic outputs (from unused autoinst outputs)`
25			`output ppi_drdy; // From port_parse_in of sd_input.v`
26			`// End of automatics`
27
28			wire [`FIB_ENTRY_SZ-1:0] ft_rdata;
29			wire [`PAR_DATA_SZ-1:0] lpp_data;
30			`/AUTOWIRE/`
31			`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
32			wire [`FIB_ASZ-1:0] ft_addr; // From fsm0 of fib_lookup_fsm.v
33	5	ghutchis	`wire ft_rd_en; // From fsm0 of fib_lookup_fsm.v`
34	4	ghutchis	wire [`FIB_ENTRY_SZ-1:0] ft_wdata; // From fsm0 of fib_lookup_fsm.v
35	5	ghutchis	`wire ft_wr_en; // From fsm0 of fib_lookup_fsm.v`
36	4	ghutchis	wire [`NUM_PORTS-1:0] lout_data; // From fsm0 of fib_lookup_fsm.v
37			`wire lout_drdy; // From fib_res_out of sd_mirror.v`
38	5	ghutchis	wire [`NUM_PORTS-1:0] lout_dst_vld; // From fsm0 of fib_lookup_fsm.v
39	4	ghutchis	`wire lout_srdy; // From fsm0 of fib_lookup_fsm.v`
40			`wire lpp_drdy; // From fsm0 of fib_lookup_fsm.v`
41			`wire lpp_srdy; // From port_parse_in of sd_input.v`
42			`// End of automatics`
43
44			`/* sd_input AUTO_TEMPLATE`
45			`(`
46			`.c_\(.*\) (ppi_\1),`
47			`.ip_\(.*\) (lpp_\1),`
48			`);`
49			`*/`
50			sd_input #(`PAR_DATA_SZ) port_parse_in
51			`(/AUTOINST/`
52			`// Outputs`
53			`.c_drdy (ppi_drdy), // Templated`
54			`.ip_srdy (lpp_srdy), // Templated`
55			`.ip_data (lpp_data), // Templated`
56			`// Inputs`
57			`.clk (clk),`
58			`.reset (reset),`
59			`.c_srdy (ppi_srdy), // Templated`
60			`.c_data (ppi_data), // Templated`
61			`.ip_drdy (lpp_drdy)); // Templated`
62
63			`/* behave1p_mem AUTO_TEMPLATE`
64			`(`
65			`.d_out (ft_rdata),`
66			`.d_in (ft_wdata),`
67			`.clk (clk),`
68			`.\(.*\) (ft_\1),`
69			`);`
70			`*/`
71			behave1p_mem #(`FIB_ENTRIES, `FIB_ENTRY_SZ) fib_mem
72			`(/AUTOINST/`
73			`// Outputs`
74			`.d_out (ft_rdata), // Templated`
75			`// Inputs`
76	5	ghutchis	`.wr_en (ft_wr_en), // Templated`
77			`.rd_en (ft_rd_en), // Templated`
78	4	ghutchis	`.clk (clk), // Templated`
79			`.d_in (ft_wdata), // Templated`
80			`.addr (ft_addr)); // Templated`
81
82			`fib_lookup_fsm fsm0`
83			`(/AUTOINST/`
84			`// Outputs`
85			`.lpp_drdy (lpp_drdy),`
86			.ft_wdata (ft_wdata[`FIB_ENTRY_SZ-1:0]),
87	5	ghutchis	`.ft_rd_en (ft_rd_en),`
88			`.ft_wr_en (ft_wr_en),`
89	4	ghutchis	.ft_addr (ft_addr[`FIB_ASZ-1:0]),
90			.lout_data (lout_data[`NUM_PORTS-1:0]),
91			`.lout_srdy (lout_srdy),`
92	5	ghutchis	.lout_dst_vld (lout_dst_vld[`NUM_PORTS-1:0]),
93	4	ghutchis	`// Inputs`
94			`.clk (clk),`
95			`.reset (reset),`
96			.lpp_data (lpp_data[`PAR_DATA_SZ-1:0]),
97			`.lpp_srdy (lpp_srdy),`
98			.ft_rdata (ft_rdata[`FIB_ENTRY_SZ-1:0]),
99			`.lout_drdy (lout_drdy));`
100
101			`/* sd_mirror AUTO_TEMPLATE`
102			`(`
103			`.c_\(.*\) (lout_\1),`
104			`.p_\(.*\) (flo_\1),`
105			`)`
106			`*/`
107			sd_mirror #(`NUM_PORTS, `NUM_PORTS) fib_res_out
108			`(/AUTOINST/`
109			`// Outputs`
110			`.c_drdy (lout_drdy), // Templated`
111			`.p_srdy (flo_srdy), // Templated`
112			`.p_data (flo_data), // Templated`
113			`// Inputs`
114			`.clk (clk),`
115			`.reset (reset),`
116			`.c_srdy (lout_srdy), // Templated`
117			`.c_data (lout_data), // Templated`
118	5	ghutchis	`.c_dst_vld (lout_dst_vld), // Templated`
119	4	ghutchis	`.p_drdy (flo_drdy)); // Templated`
120
121			`endmodule // fib_lookup`
122	5	ghutchis	`// Local Variables:`
123			`// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")`
124			`// End:`

Browse

Tools

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [fib_lookup.v] - Blame information for rev 5