OpenCores
URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [port_clocking.v] - Blame information for rev 8

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 8 ghutchis
module port_clocking
2
  (input         clk,
3
   input         reset,
4
   input         gmii_rx_clk,
5
   output        gmii_rx_reset
6
   );
7
 
8
  // if this were a testable design, clock muxing logic would go here as well
9
 
10
  reg            rx_sync1, rx_sync2;
11
 
12
  always @(posedge gmii_rx_clk)
13
    begin
14
      rx_sync1 <= #1 reset;
15
      rx_sync2 <= #1 rx_sync1;
16
    end
17
 
18
  assign gmii_rx_reset = reset | rx_sync2;
19
 
20
endmodule // port_clocking

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.