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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [port_macro.v] - Blame information for rev 8

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module port_macro
  (input         clk,
   input         reset,
 
   input [`PRW_SZ-1:0]   ri_data,                // To ring_tap of port_ring_tap.v
   output [`PRW_SZ-1:0]  ro_data,                // From ring_tap of port_ring_tap.v
   input [`NUM_PORTS-1:0] fli_data,              // To ring_tap of port_ring_tap.v
   /*AUTOINPUT*/
   // Beginning of automatic inputs (from unused autoinst inputs)
   input                fli_srdy,               // To ring_tap of port_ring_tap.v
   input                gmii_rx_clk,            // To port_clocking of port_clocking.v, ...
   input                gmii_rx_dv,             // To rx_gigmac of sd_rx_gigmac.v
   input [7:0]           gmii_rxd,               // To rx_gigmac of sd_rx_gigmac.v
   input                p2f_drdy,               // To pkt_parse of pkt_parse.v
   input                ri_srdy,                // To ring_tap of port_ring_tap.v
   input                ro_drdy,                // To ring_tap of port_ring_tap.v
   // End of automatics
 
   output               fli_drdy,               // From ring_tap of port_ring_tap.v
   output               gmii_tx_dv,             // From tx_gmii of sd_tx_gigmac.v
   output [7:0]          gmii_txd,               // From tx_gmii of sd_tx_gigmac.v
   output [`PAR_DATA_SZ-1:0] p2f_data,           // From pkt_parse of pkt_parse.v
   output               p2f_srdy,               // From pkt_parse of pkt_parse.v
   output               ri_drdy,                // From ring_tap of port_ring_tap.v
   output               ro_srdy                 // From ring_tap of port_ring_tap.v
   );
 
  wire [`RX_USG_SZ-1:0] rx_usage;
  wire [`TX_USG_SZ-1:0] tx_usage;
  wire [`PFW_SZ-1:0]     prx_data;               // From fifo_rx of sd_fifo_b.v
  wire [`PFW_SZ-1:0]     ptx_data;               // From fifo_tx of sd_fifo_b.v
  wire [`PFW_SZ-1:0]     rttx_data;              // From ring_tap of port_ring_tap.v
  wire [1:0]             rxg_code;               // From rx_sync_fifo of sd_fifo_s.v
  wire [7:0]             rxg_data;               // From rx_sync_fifo of sd_fifo_s.v
  wire [`PFW_SZ-1:0]     ctx_data;               // From oflow of egr_oflow.v
  /*AUTOWIRE*/
  // Beginning of automatic wires (for undeclared instantiated-module outputs)
  wire                  crx_abort;              // From con of concentrator.v
  wire                  crx_commit;             // From con of concentrator.v
  wire [`PFW_SZ-1:0]     crx_data;               // From con of concentrator.v
  wire                  crx_drdy;               // From fifo_rx of sd_fifo_b.v
  wire                  crx_srdy;               // From con of concentrator.v
  wire                  ctx_abort;              // From oflow of egr_oflow.v
  wire                  ctx_commit;             // From oflow of egr_oflow.v
  wire                  ctx_drdy;               // From fifo_tx of sd_fifo_b.v
  wire                  ctx_srdy;               // From oflow of egr_oflow.v
  wire                  gmii_rx_reset;          // From port_clocking of port_clocking.v
  wire [1:0]             pdo_code;               // From pkt_parse of pkt_parse.v
  wire [7:0]             pdo_data;               // From pkt_parse of pkt_parse.v
  wire                  pdo_drdy;               // From con of concentrator.v
  wire                  pdo_srdy;               // From pkt_parse of pkt_parse.v
  wire                  prx_drdy;               // From ring_tap of port_ring_tap.v
  wire                  prx_srdy;               // From fifo_rx of sd_fifo_b.v
  wire                  ptx_drdy;               // From dst of distributor.v
  wire                  ptx_srdy;               // From fifo_tx of sd_fifo_b.v
  wire                  rttx_drdy;              // From oflow of egr_oflow.v
  wire                  rttx_srdy;              // From ring_tap of port_ring_tap.v
  wire [1:0]             rxc_rxg_code;           // From rx_gigmac of sd_rx_gigmac.v
  wire [7:0]             rxc_rxg_data;           // From rx_gigmac of sd_rx_gigmac.v
  wire                  rxc_rxg_drdy;           // From rx_sync_fifo of sd_fifo_s.v
  wire                  rxc_rxg_srdy;           // From rx_gigmac of sd_rx_gigmac.v
  wire                  rxg_drdy;               // From pkt_parse of pkt_parse.v
  wire                  rxg_srdy;               // From rx_sync_fifo of sd_fifo_s.v
  wire [1:0]             txg_code;               // From dst of distributor.v
  wire [7:0]             txg_data;               // From dst of distributor.v
  wire                  txg_drdy;               // From tx_gmii of sd_tx_gigmac.v
  wire                  txg_srdy;               // From dst of distributor.v
  // End of automatics
 
 
  port_clocking port_clocking
    (/*AUTOINST*/
     // Outputs
     .gmii_rx_reset                     (gmii_rx_reset),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .gmii_rx_clk                       (gmii_rx_clk));
 
/*  sd_rx_gigmac AUTO_TEMPLATE
 (
   .clk                         (gmii_rx_clk),
   .reset                       (gmii_rx_reset),
   .rxg_\(.*\)                  (rxc_rxg_\1[]),
 );
 */
  sd_rx_gigmac rx_gigmac
    (/*AUTOINST*/
     // Outputs
     .rxg_srdy                          (rxc_rxg_srdy),          // Templated
     .rxg_code                          (rxc_rxg_code[1:0]),      // Templated
     .rxg_data                          (rxc_rxg_data[7:0]),      // Templated
     // Inputs
     .clk                               (gmii_rx_clk),           // Templated
     .reset                             (gmii_rx_reset),         // Templated
     .gmii_rx_dv                        (gmii_rx_dv),
     .gmii_rxd                          (gmii_rxd[7:0]),
     .rxg_drdy                          (rxc_rxg_drdy));                 // Templated
 
/* sd_fifo_s AUTO_TEMPLATE
 (
     .c_clk                             (gmii_rx_clk),
     .c_reset                           (gmii_rx_reset),
     .c_data                            ({rxc_rxg_code,rxc_rxg_data}),
     .p_data                            ({rxg_code,rxg_data}),
     .p_clk                             (clk),
     .p_reset                           (reset),
  .c_\(.*\)                     (rxc_rxg_\1[]),
  .p_\(.*\)                     (rxg_\1[]),
 );
 */
  sd_fifo_s #(8+2,16,1) rx_sync_fifo
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (rxc_rxg_drdy),          // Templated
     .p_srdy                            (rxg_srdy),              // Templated
     .p_data                            ({rxg_code,rxg_data}),   // Templated
     // Inputs
     .c_clk                             (gmii_rx_clk),           // Templated
     .c_reset                           (gmii_rx_reset),         // Templated
     .c_srdy                            (rxc_rxg_srdy),          // Templated
     .c_data                            ({rxc_rxg_code,rxc_rxg_data}), // Templated
     .p_clk                             (clk),                   // Templated
     .p_reset                           (reset),                 // Templated
     .p_drdy                            (rxg_drdy));             // Templated
 
  pkt_parse pkt_parse
    (/*AUTOINST*/
     // Outputs
     .rxg_drdy                          (rxg_drdy),
     .p2f_srdy                          (p2f_srdy),
     .p2f_data                          (p2f_data[`PAR_DATA_SZ-1:0]),
     .pdo_srdy                          (pdo_srdy),
     .pdo_code                          (pdo_code[1:0]),
     .pdo_data                          (pdo_data[7:0]),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .rxg_srdy                          (rxg_srdy),
     .rxg_code                          (rxg_code[1:0]),
     .rxg_data                          (rxg_data[7:0]),
     .p2f_drdy                          (p2f_drdy),
     .pdo_drdy                          (pdo_drdy));
 
/* concentrator AUTO_TEMPLATE
 (
    .c_\(.*\)     (pdo_\1[]),
    .p_\(.*\)     (crx_\1[]),
 );
 */
  concentrator con
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (pdo_drdy),              // Templated
     .p_data                            (crx_data[`PFW_SZ-1:0]), // Templated
     .p_srdy                            (crx_srdy),              // Templated
     .p_commit                          (crx_commit),            // Templated
     .p_abort                           (crx_abort),             // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_data                            (pdo_data[7:0]),  // Templated
     .c_code                            (pdo_code[1:0]),  // Templated
     .c_srdy                            (pdo_srdy),              // Templated
     .p_drdy                            (crx_drdy));             // Templated
 
  /* sd_fifo_b AUTO_TEMPLATE "fifo_\(.*\)"
   (
    .p_abort  (1'b0),
    .p_commit (1'b0),
    .usage    (@_usage),
    .c_\(.*\)     (c@_\1),
    .p_\(.*\)    (p@_\1),
   );
   */
  sd_fifo_b #(`PFW_SZ, `RX_FIFO_DEPTH, 0, 1) fifo_rx
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (crx_drdy),              // Templated
     .p_srdy                            (prx_srdy),              // Templated
     .p_data                            (prx_data),              // Templated
     .usage                             (rx_usage),              // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (crx_srdy),              // Templated
     .c_commit                          (crx_commit),            // Templated
     .c_abort                           (crx_abort),             // Templated
     .c_data                            (crx_data),              // Templated
     .p_drdy                            (prx_drdy),              // Templated
     .p_commit                          (1'b0),                  // Templated
     .p_abort                           (1'b0));                         // Templated
 
  sd_fifo_b #(`PFW_SZ, `TX_FIFO_DEPTH, 0, 1) fifo_tx
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (ctx_drdy),              // Templated
     .p_srdy                            (ptx_srdy),              // Templated
     .p_data                            (ptx_data),              // Templated
     .usage                             (tx_usage),              // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (ctx_srdy),              // Templated
     .c_commit                          (ctx_commit),            // Templated
     .c_abort                           (ctx_abort),             // Templated
     .c_data                            (ctx_data),              // Templated
     .p_drdy                            (ptx_drdy),              // Templated
     .p_commit                          (1'b0),                  // Templated
     .p_abort                           (1'b0));                         // Templated
 
/* port_ring_tap AUTO_TEMPLATE
 (
    .ro_data                            (ro_data[`PRW_SZ-1:0]),
    .ri_data                            (ri_data[`PRW_SZ-1:0]),
    .prx_\(.*\)    (prx_\1),
    .ptx_\(.*\)    (rttx_\1),
  );
 */
  port_ring_tap ring_tap
    (/*AUTOINST*/
     // Outputs
     .ri_drdy                           (ri_drdy),
     .prx_drdy                          (prx_drdy),              // Templated
     .ro_srdy                           (ro_srdy),
     .ro_data                           (ro_data[`PRW_SZ-1:0]),   // Templated
     .ptx_srdy                          (rttx_srdy),             // Templated
     .ptx_data                          (rttx_data),             // Templated
     .fli_drdy                          (fli_drdy),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .ri_srdy                           (ri_srdy),
     .ri_data                           (ri_data[`PRW_SZ-1:0]),   // Templated
     .prx_srdy                          (prx_srdy),              // Templated
     .prx_data                          (prx_data),              // Templated
     .ro_drdy                           (ro_drdy),
     .ptx_drdy                          (rttx_drdy),             // Templated
     .fli_srdy                          (fli_srdy),
     .fli_data                          (fli_data[`NUM_PORTS-1:0]));
 
/* egr_oflow AUTO_TEMPLATE
 (
    .c_\(.*\)    (rttx_\1[]),
    .p_\(.*\)    (ctx_\1[]),
  );
 */
  egr_oflow oflow
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (rttx_drdy),             // Templated
     .p_srdy                            (ctx_srdy),              // Templated
     .p_data                            (ctx_data[`PFW_SZ-1:0]), // Templated
     .p_commit                          (ctx_commit),            // Templated
     .p_abort                           (ctx_abort),             // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (rttx_srdy),             // Templated
     .c_data                            (rttx_data[`PFW_SZ-1:0]), // Templated
     .tx_usage                          (tx_usage[`TX_USG_SZ-1:0]),
     .p_drdy                            (ctx_drdy));             // Templated
 
/* distributor AUTO_TEMPLATE
 (
    .p_\(.*\)    (txg_\1[]),
 );
 */
  distributor dst
    (/*AUTOINST*/
     // Outputs
     .ptx_drdy                          (ptx_drdy),
     .p_srdy                            (txg_srdy),              // Templated
     .p_code                            (txg_code[1:0]),  // Templated
     .p_data                            (txg_data[7:0]),  // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .ptx_srdy                          (ptx_srdy),
     .ptx_data                          (ptx_data[`PFW_SZ-1:0]),
     .p_drdy                            (txg_drdy));             // Templated
 
  sd_tx_gigmac tx_gmii
    (/*AUTOINST*/
     // Outputs
     .gmii_tx_dv                        (gmii_tx_dv),
     .gmii_txd                          (gmii_txd[7:0]),
     .txg_drdy                          (txg_drdy),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .txg_srdy                          (txg_srdy),
     .txg_code                          (txg_code[1:0]),
     .txg_data                          (txg_data[7:0]));
 
endmodule // port_macro
// Local Variables:
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/forks")
// End:  

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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [port_macro.v] - Blame information for rev 8

Line No.	Rev	Author	Line
1	8	ghutchis	`module port_macro`
2			`(input clk,`
3			`input reset,`
4
5			input [`PRW_SZ-1:0] ri_data, // To ring_tap of port_ring_tap.v
6			output [`PRW_SZ-1:0] ro_data, // From ring_tap of port_ring_tap.v
7			input [`NUM_PORTS-1:0] fli_data, // To ring_tap of port_ring_tap.v
8			`/AUTOINPUT/`
9			`// Beginning of automatic inputs (from unused autoinst inputs)`
10			`input fli_srdy, // To ring_tap of port_ring_tap.v`
11			`input gmii_rx_clk, // To port_clocking of port_clocking.v, ...`
12			`input gmii_rx_dv, // To rx_gigmac of sd_rx_gigmac.v`
13			`input [7:0] gmii_rxd, // To rx_gigmac of sd_rx_gigmac.v`
14			`input p2f_drdy, // To pkt_parse of pkt_parse.v`
15			`input ri_srdy, // To ring_tap of port_ring_tap.v`
16			`input ro_drdy, // To ring_tap of port_ring_tap.v`
17			`// End of automatics`
18
19			`output fli_drdy, // From ring_tap of port_ring_tap.v`
20			`output gmii_tx_dv, // From tx_gmii of sd_tx_gigmac.v`
21			`output [7:0] gmii_txd, // From tx_gmii of sd_tx_gigmac.v`
22			output [`PAR_DATA_SZ-1:0] p2f_data, // From pkt_parse of pkt_parse.v
23			`output p2f_srdy, // From pkt_parse of pkt_parse.v`
24			`output ri_drdy, // From ring_tap of port_ring_tap.v`
25			`output ro_srdy // From ring_tap of port_ring_tap.v`
26			`);`
27
28			wire [`RX_USG_SZ-1:0] rx_usage;
29			wire [`TX_USG_SZ-1:0] tx_usage;
30			wire [`PFW_SZ-1:0] prx_data; // From fifo_rx of sd_fifo_b.v
31			wire [`PFW_SZ-1:0] ptx_data; // From fifo_tx of sd_fifo_b.v
32			wire [`PFW_SZ-1:0] rttx_data; // From ring_tap of port_ring_tap.v
33			`wire [1:0] rxg_code; // From rx_sync_fifo of sd_fifo_s.v`
34			`wire [7:0] rxg_data; // From rx_sync_fifo of sd_fifo_s.v`
35			wire [`PFW_SZ-1:0] ctx_data; // From oflow of egr_oflow.v
36			`/AUTOWIRE/`
37			`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
38			`wire crx_abort; // From con of concentrator.v`
39			`wire crx_commit; // From con of concentrator.v`
40			wire [`PFW_SZ-1:0] crx_data; // From con of concentrator.v
41			`wire crx_drdy; // From fifo_rx of sd_fifo_b.v`
42			`wire crx_srdy; // From con of concentrator.v`
43			`wire ctx_abort; // From oflow of egr_oflow.v`
44			`wire ctx_commit; // From oflow of egr_oflow.v`
45			`wire ctx_drdy; // From fifo_tx of sd_fifo_b.v`
46			`wire ctx_srdy; // From oflow of egr_oflow.v`
47			`wire gmii_rx_reset; // From port_clocking of port_clocking.v`
48			`wire [1:0] pdo_code; // From pkt_parse of pkt_parse.v`
49			`wire [7:0] pdo_data; // From pkt_parse of pkt_parse.v`
50			`wire pdo_drdy; // From con of concentrator.v`
51			`wire pdo_srdy; // From pkt_parse of pkt_parse.v`
52			`wire prx_drdy; // From ring_tap of port_ring_tap.v`
53			`wire prx_srdy; // From fifo_rx of sd_fifo_b.v`
54			`wire ptx_drdy; // From dst of distributor.v`
55			`wire ptx_srdy; // From fifo_tx of sd_fifo_b.v`
56			`wire rttx_drdy; // From oflow of egr_oflow.v`
57			`wire rttx_srdy; // From ring_tap of port_ring_tap.v`
58			`wire [1:0] rxc_rxg_code; // From rx_gigmac of sd_rx_gigmac.v`
59			`wire [7:0] rxc_rxg_data; // From rx_gigmac of sd_rx_gigmac.v`
60			`wire rxc_rxg_drdy; // From rx_sync_fifo of sd_fifo_s.v`
61			`wire rxc_rxg_srdy; // From rx_gigmac of sd_rx_gigmac.v`
62			`wire rxg_drdy; // From pkt_parse of pkt_parse.v`
63			`wire rxg_srdy; // From rx_sync_fifo of sd_fifo_s.v`
64			`wire [1:0] txg_code; // From dst of distributor.v`
65			`wire [7:0] txg_data; // From dst of distributor.v`
66			`wire txg_drdy; // From tx_gmii of sd_tx_gigmac.v`
67			`wire txg_srdy; // From dst of distributor.v`
68			`// End of automatics`
69
70
71			`port_clocking port_clocking`
72			`(/AUTOINST/`
73			`// Outputs`
74			`.gmii_rx_reset (gmii_rx_reset),`
75			`// Inputs`
76			`.clk (clk),`
77			`.reset (reset),`
78			`.gmii_rx_clk (gmii_rx_clk));`
79
80			`/* sd_rx_gigmac AUTO_TEMPLATE`
81			`(`
82			`.clk (gmii_rx_clk),`
83			`.reset (gmii_rx_reset),`
84			`.rxg_\(.*\) (rxc_rxg_\1[]),`
85			`);`
86			`*/`
87			`sd_rx_gigmac rx_gigmac`
88			`(/AUTOINST/`
89			`// Outputs`
90			`.rxg_srdy (rxc_rxg_srdy), // Templated`
91			`.rxg_code (rxc_rxg_code[1:0]), // Templated`
92			`.rxg_data (rxc_rxg_data[7:0]), // Templated`
93			`// Inputs`
94			`.clk (gmii_rx_clk), // Templated`
95			`.reset (gmii_rx_reset), // Templated`
96			`.gmii_rx_dv (gmii_rx_dv),`
97			`.gmii_rxd (gmii_rxd[7:0]),`
98			`.rxg_drdy (rxc_rxg_drdy)); // Templated`
99
100			`/* sd_fifo_s AUTO_TEMPLATE`
101			`(`
102			`.c_clk (gmii_rx_clk),`
103			`.c_reset (gmii_rx_reset),`
104			`.c_data ({rxc_rxg_code,rxc_rxg_data}),`
105			`.p_data ({rxg_code,rxg_data}),`
106			`.p_clk (clk),`
107			`.p_reset (reset),`
108			`.c_\(.*\) (rxc_rxg_\1[]),`
109			`.p_\(.*\) (rxg_\1[]),`
110			`);`
111			`*/`
112			`sd_fifo_s #(8+2,16,1) rx_sync_fifo`
113			`(/AUTOINST/`
114			`// Outputs`
115			`.c_drdy (rxc_rxg_drdy), // Templated`
116			`.p_srdy (rxg_srdy), // Templated`
117			`.p_data ({rxg_code,rxg_data}), // Templated`
118			`// Inputs`
119			`.c_clk (gmii_rx_clk), // Templated`
120			`.c_reset (gmii_rx_reset), // Templated`
121			`.c_srdy (rxc_rxg_srdy), // Templated`
122			`.c_data ({rxc_rxg_code,rxc_rxg_data}), // Templated`
123			`.p_clk (clk), // Templated`
124			`.p_reset (reset), // Templated`
125			`.p_drdy (rxg_drdy)); // Templated`
126
127			`pkt_parse pkt_parse`
128			`(/AUTOINST/`
129			`// Outputs`
130			`.rxg_drdy (rxg_drdy),`
131			`.p2f_srdy (p2f_srdy),`
132			.p2f_data (p2f_data[`PAR_DATA_SZ-1:0]),
133			`.pdo_srdy (pdo_srdy),`
134			`.pdo_code (pdo_code[1:0]),`
135			`.pdo_data (pdo_data[7:0]),`
136			`// Inputs`
137			`.clk (clk),`
138			`.reset (reset),`
139			`.rxg_srdy (rxg_srdy),`
140			`.rxg_code (rxg_code[1:0]),`
141			`.rxg_data (rxg_data[7:0]),`
142			`.p2f_drdy (p2f_drdy),`
143			`.pdo_drdy (pdo_drdy));`
144
145			`/* concentrator AUTO_TEMPLATE`
146			`(`
147			`.c_\(.*\) (pdo_\1[]),`
148			`.p_\(.*\) (crx_\1[]),`
149			`);`
150			`*/`
151			`concentrator con`
152			`(/AUTOINST/`
153			`// Outputs`
154			`.c_drdy (pdo_drdy), // Templated`
155			.p_data (crx_data[`PFW_SZ-1:0]), // Templated
156			`.p_srdy (crx_srdy), // Templated`
157			`.p_commit (crx_commit), // Templated`
158			`.p_abort (crx_abort), // Templated`
159			`// Inputs`
160			`.clk (clk),`
161			`.reset (reset),`
162			`.c_data (pdo_data[7:0]), // Templated`
163			`.c_code (pdo_code[1:0]), // Templated`
164			`.c_srdy (pdo_srdy), // Templated`
165			`.p_drdy (crx_drdy)); // Templated`
166
167			`/* sd_fifo_b AUTO_TEMPLATE "fifo_\(.*\)"`
168			`(`
169			`.p_abort (1'b0),`
170			`.p_commit (1'b0),`
171			`.usage (@_usage),`
172			`.c_\(.*\) (c@_\1),`
173			`.p_\(.*\) (p@_\1),`
174			`);`
175			`*/`
176			sd_fifo_b #(`PFW_SZ, `RX_FIFO_DEPTH, 0, 1) fifo_rx
177			`(/AUTOINST/`
178			`// Outputs`
179			`.c_drdy (crx_drdy), // Templated`
180			`.p_srdy (prx_srdy), // Templated`
181			`.p_data (prx_data), // Templated`
182			`.usage (rx_usage), // Templated`
183			`// Inputs`
184			`.clk (clk),`
185			`.reset (reset),`
186			`.c_srdy (crx_srdy), // Templated`
187			`.c_commit (crx_commit), // Templated`
188			`.c_abort (crx_abort), // Templated`
189			`.c_data (crx_data), // Templated`
190			`.p_drdy (prx_drdy), // Templated`
191			`.p_commit (1'b0), // Templated`
192			`.p_abort (1'b0)); // Templated`
193
194			sd_fifo_b #(`PFW_SZ, `TX_FIFO_DEPTH, 0, 1) fifo_tx
195			`(/AUTOINST/`
196			`// Outputs`
197			`.c_drdy (ctx_drdy), // Templated`
198			`.p_srdy (ptx_srdy), // Templated`
199			`.p_data (ptx_data), // Templated`
200			`.usage (tx_usage), // Templated`
201			`// Inputs`
202			`.clk (clk),`
203			`.reset (reset),`
204			`.c_srdy (ctx_srdy), // Templated`
205			`.c_commit (ctx_commit), // Templated`
206			`.c_abort (ctx_abort), // Templated`
207			`.c_data (ctx_data), // Templated`
208			`.p_drdy (ptx_drdy), // Templated`
209			`.p_commit (1'b0), // Templated`
210			`.p_abort (1'b0)); // Templated`
211
212			`/* port_ring_tap AUTO_TEMPLATE`
213			`(`
214			.ro_data (ro_data[`PRW_SZ-1:0]),
215			.ri_data (ri_data[`PRW_SZ-1:0]),
216			`.prx_\(.*\) (prx_\1),`
217			`.ptx_\(.*\) (rttx_\1),`
218			`);`
219			`*/`
220			`port_ring_tap ring_tap`
221			`(/AUTOINST/`
222			`// Outputs`
223			`.ri_drdy (ri_drdy),`
224			`.prx_drdy (prx_drdy), // Templated`
225			`.ro_srdy (ro_srdy),`
226			.ro_data (ro_data[`PRW_SZ-1:0]), // Templated
227			`.ptx_srdy (rttx_srdy), // Templated`
228			`.ptx_data (rttx_data), // Templated`
229			`.fli_drdy (fli_drdy),`
230			`// Inputs`
231			`.clk (clk),`
232			`.reset (reset),`
233			`.ri_srdy (ri_srdy),`
234			.ri_data (ri_data[`PRW_SZ-1:0]), // Templated
235			`.prx_srdy (prx_srdy), // Templated`
236			`.prx_data (prx_data), // Templated`
237			`.ro_drdy (ro_drdy),`
238			`.ptx_drdy (rttx_drdy), // Templated`
239			`.fli_srdy (fli_srdy),`
240			.fli_data (fli_data[`NUM_PORTS-1:0]));
241
242			`/* egr_oflow AUTO_TEMPLATE`
243			`(`
244			`.c_\(.*\) (rttx_\1[]),`
245			`.p_\(.*\) (ctx_\1[]),`
246			`);`
247			`*/`
248			`egr_oflow oflow`
249			`(/AUTOINST/`
250			`// Outputs`
251			`.c_drdy (rttx_drdy), // Templated`
252			`.p_srdy (ctx_srdy), // Templated`
253			.p_data (ctx_data[`PFW_SZ-1:0]), // Templated
254			`.p_commit (ctx_commit), // Templated`
255			`.p_abort (ctx_abort), // Templated`
256			`// Inputs`
257			`.clk (clk),`
258			`.reset (reset),`
259			`.c_srdy (rttx_srdy), // Templated`
260			.c_data (rttx_data[`PFW_SZ-1:0]), // Templated
261			.tx_usage (tx_usage[`TX_USG_SZ-1:0]),
262			`.p_drdy (ctx_drdy)); // Templated`
263
264			`/* distributor AUTO_TEMPLATE`
265			`(`
266			`.p_\(.*\) (txg_\1[]),`
267			`);`
268			`*/`
269			`distributor dst`
270			`(/AUTOINST/`
271			`// Outputs`
272			`.ptx_drdy (ptx_drdy),`
273			`.p_srdy (txg_srdy), // Templated`
274			`.p_code (txg_code[1:0]), // Templated`
275			`.p_data (txg_data[7:0]), // Templated`
276			`// Inputs`
277			`.clk (clk),`
278			`.reset (reset),`
279			`.ptx_srdy (ptx_srdy),`
280			.ptx_data (ptx_data[`PFW_SZ-1:0]),
281			`.p_drdy (txg_drdy)); // Templated`
282
283			`sd_tx_gigmac tx_gmii`
284			`(/AUTOINST/`
285			`// Outputs`
286			`.gmii_tx_dv (gmii_tx_dv),`
287			`.gmii_txd (gmii_txd[7:0]),`
288			`.txg_drdy (txg_drdy),`
289			`// Inputs`
290			`.clk (clk),`
291			`.reset (reset),`
292			`.txg_srdy (txg_srdy),`
293			`.txg_code (txg_code[1:0]),`
294			`.txg_data (txg_data[7:0]));`
295
296			`endmodule // port_macro`
297			`// Local Variables:`
298			`// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/forks")`
299			`// End:`