URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [port_ring_tap.v] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log


// Inputs are ri (Ring In), ro (Ring Out),
// fli (FIB lookup in), prx (port in/RX), and ptx (port out/TX)
 
module port_ring_tap
  #(parameter rdp_sz = 64,
    parameter portnum = 0)
  (
   input         clk,
   input         reset,
 
   input         ri_srdy,
   output        ri_drdy,
   input [rdp_sz-1:0] ri_data,
 
   input         prx_srdy,
   output        prx_drdy,
   input [rdp_sz-1:0] prx_data,
 
   output        ro_srdy,
   input         ro_drdy,
   output [rdp_sz-1:0] ro_data,
 
   output        ptx_srdy,
   input         ptx_drdy,
   output [rdp_sz-1:0] ptx_data,
 
   input         fli_srdy,
   output        fli_drdy,
   input [`NUM_PORTS-1:0] fli_data
   );
 
  /*AUTOWIRE*/
 
  /* sd_input AUTO_TEMPLATE "tc_\(.*\)"
   (
    .c_\(.*\)     (@_\1[]),
    .ip_\(.*\)    (l@_\1[]),
   );
   */
 
  sd_input #(rdp_sz) tc_ri
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (ri_drdy),               // Templated
     .ip_srdy                           (lri_srdy),              // Templated
     .ip_data                           (lri_data[width-1:0]),   // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (ri_srdy),               // Templated
     .c_data                            (ri_data[width-1:0]),    // Templated
     .ip_drdy                           (lri_drdy));              // Templated
 
  sd_input #(rdp_sz) tc_prx
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (prx_drdy),              // Templated
     .ip_srdy                           (lprx_srdy),             // Templated
     .ip_data                           (lprx_data[width-1:0]),  // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (prx_srdy),              // Templated
     .c_data                            (prx_data[width-1:0]),   // Templated
     .ip_drdy                           (lprx_drdy));             // Templated
 
  sd_input #(`NUM_PORTS) tc_fli
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (fli_drdy),              // Templated
     .ip_srdy                           (lfli_srdy),             // Templated
     .ip_data                           (lfli_data[width-1:0]),  // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (fli_srdy),              // Templated
     .c_data                            (fli_data[width-1:0]),   // Templated
     .ip_drdy                           (lfli_drdy));             // Templated
 
  /* sd_output AUTO_TEMPLATE "tc_\(.*\)"
   (
    .ic_\(.*\)    (l@_\1[]),
    .p_\(.*\)     (@_\1[]),
   );
   */
 
  sd_output #(rdp_sz) tc_ptx
    (/*AUTOINST*/
     // Outputs
     .ic_drdy                           (lptx_drdy),             // Templated
     .p_srdy                            (ptx_srdy),              // Templated
     .p_data                            (ptx_data[width-1:0]),   // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .ic_srdy                           (lptx_srdy),             // Templated
     .ic_data                           (lptx_data[width-1:0]),  // Templated
     .p_drdy                            (ptx_drdy));              // Templated
 
  sd_output #(rdp_sz) tc_ro
    (/*AUTOINST*/
     // Outputs
     .ic_drdy                           (lro_drdy),              // Templated
     .p_srdy                            (ro_srdy),               // Templated
     .p_data                            (ro_data[width-1:0]),    // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .ic_srdy                           (lro_srdy),              // Templated
     .ic_data                           (lro_data[width-1:0]),   // Templated
     .p_drdy                            (ro_drdy));               // Templated
 
endmodule // port_ring_tap
// Local Variables:
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
// End:  

Line No.	Rev	Author	Line
1	5	ghutchis	`// Inputs are ri (Ring In), ro (Ring Out),`
2			`// fli (FIB lookup in), prx (port in/RX), and ptx (port out/TX)`
3
4			`module port_ring_tap`
5			`#(parameter rdp_sz = 64,`
6			`parameter portnum = 0)`
7			`(`
8			`input clk,`
9			`input reset,`
10
11			`input ri_srdy,`
12			`output ri_drdy,`
13			`input [rdp_sz-1:0] ri_data,`
14
15			`input prx_srdy,`
16			`output prx_drdy,`
17			`input [rdp_sz-1:0] prx_data,`
18
19			`output ro_srdy,`
20			`input ro_drdy,`
21			`output [rdp_sz-1:0] ro_data,`
22
23			`output ptx_srdy,`
24			`input ptx_drdy,`
25			`output [rdp_sz-1:0] ptx_data,`
26
27			`input fli_srdy,`
28			`output fli_drdy,`
29			input [`NUM_PORTS-1:0] fli_data
30			`);`
31
32			`/AUTOWIRE/`
33
34			`/* sd_input AUTO_TEMPLATE "tc_\(.*\)"`
35			`(`
36			`.c_\(.*\) (@_\1[]),`
37			`.ip_\(.*\) (l@_\1[]),`
38			`);`
39			`*/`
40
41			`sd_input #(rdp_sz) tc_ri`
42			`(/AUTOINST/`
43			`// Outputs`
44			`.c_drdy (ri_drdy), // Templated`
45			`.ip_srdy (lri_srdy), // Templated`
46			`.ip_data (lri_data[width-1:0]), // Templated`
47			`// Inputs`
48			`.clk (clk),`
49			`.reset (reset),`
50			`.c_srdy (ri_srdy), // Templated`
51			`.c_data (ri_data[width-1:0]), // Templated`
52			`.ip_drdy (lri_drdy)); // Templated`
53
54			`sd_input #(rdp_sz) tc_prx`
55			`(/AUTOINST/`
56			`// Outputs`
57			`.c_drdy (prx_drdy), // Templated`
58			`.ip_srdy (lprx_srdy), // Templated`
59			`.ip_data (lprx_data[width-1:0]), // Templated`
60			`// Inputs`
61			`.clk (clk),`
62			`.reset (reset),`
63			`.c_srdy (prx_srdy), // Templated`
64			`.c_data (prx_data[width-1:0]), // Templated`
65			`.ip_drdy (lprx_drdy)); // Templated`
66
67			sd_input #(`NUM_PORTS) tc_fli
68			`(/AUTOINST/`
69			`// Outputs`
70			`.c_drdy (fli_drdy), // Templated`
71			`.ip_srdy (lfli_srdy), // Templated`
72			`.ip_data (lfli_data[width-1:0]), // Templated`
73			`// Inputs`
74			`.clk (clk),`
75			`.reset (reset),`
76			`.c_srdy (fli_srdy), // Templated`
77			`.c_data (fli_data[width-1:0]), // Templated`
78			`.ip_drdy (lfli_drdy)); // Templated`
79
80			`/* sd_output AUTO_TEMPLATE "tc_\(.*\)"`
81			`(`
82			`.ic_\(.*\) (l@_\1[]),`
83			`.p_\(.*\) (@_\1[]),`
84			`);`
85			`*/`
86
87			`sd_output #(rdp_sz) tc_ptx`
88			`(/AUTOINST/`
89			`// Outputs`
90			`.ic_drdy (lptx_drdy), // Templated`
91			`.p_srdy (ptx_srdy), // Templated`
92			`.p_data (ptx_data[width-1:0]), // Templated`
93			`// Inputs`
94			`.clk (clk),`
95			`.reset (reset),`
96			`.ic_srdy (lptx_srdy), // Templated`
97			`.ic_data (lptx_data[width-1:0]), // Templated`
98			`.p_drdy (ptx_drdy)); // Templated`
99
100			`sd_output #(rdp_sz) tc_ro`
101			`(/AUTOINST/`
102			`// Outputs`
103			`.ic_drdy (lro_drdy), // Templated`
104			`.p_srdy (ro_srdy), // Templated`
105			`.p_data (ro_data[width-1:0]), // Templated`
106			`// Inputs`
107			`.clk (clk),`
108			`.reset (reset),`
109			`.ic_srdy (lro_srdy), // Templated`
110			`.ic_data (lro_data[width-1:0]), // Templated`
111			`.p_drdy (ro_drdy)); // Templated`
112
113			`endmodule // port_ring_tap`
114			`// Local Variables:`
115			`// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")`
116			`// End:`

Browse

Tools

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [port_ring_tap.v] - Blame information for rev 5