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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [port_ring_tap.v] - Blame information for rev 8

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// Inputs are ri (Ring In), ro (Ring Out),
// fli (FIB lookup in), prx (port in/RX), and ptx (port out/TX)
 
module port_ring_tap
  #(parameter rdp_sz = `PRW_SZ,
    parameter pdp_sz = `PFW_SZ,
    parameter portnum = 0)
  (
   input         clk,
   input         reset,
 
   input         ri_srdy,
   output        ri_drdy,
   input [rdp_sz-1:0] ri_data,
 
   input         prx_srdy,
   output        prx_drdy,
   input [pdp_sz-1:0] prx_data,
 
   output        ro_srdy,
   input         ro_drdy,
   output [rdp_sz-1:0] ro_data,
 
   output        ptx_srdy,
   input         ptx_drdy,
   output [pdp_sz-1:0] ptx_data,
 
   input         fli_srdy,
   output        fli_drdy,
   input [`NUM_PORTS-1:0] fli_data
   );
 
  wire [`PRW_SZ-1:0]     lri_data;               // From tc_ri of sd_input.v
  wire [`NUM_PORTS-1:0]  lfli_data;              // From tc_fli of sd_input.v
  wire [`PFW_SZ-1:0]     lprx_data;              // From tc_prx of sd_input.v
  wire [`PFW_SZ-1:0]     lptx_data;              // From fsm of port_ring_tap_fsm.v
  wire [`PRW_SZ-1:0]     lro_data;               // From fsm of port_ring_tap_fsm.v
  /*AUTOWIRE*/
  // Beginning of automatic wires (for undeclared instantiated-module outputs)
  wire                  lfli_drdy;              // From fsm of port_ring_tap_fsm.v
  wire                  lfli_srdy;              // From tc_fli of sd_input.v
  wire                  lprx_drdy;              // From fsm of port_ring_tap_fsm.v
  wire                  lprx_srdy;              // From tc_prx of sd_input.v
  wire                  lptx_drdy;              // From tc_ptx of sd_output.v
  wire                  lptx_srdy;              // From fsm of port_ring_tap_fsm.v
  wire                  lri_drdy;               // From fsm of port_ring_tap_fsm.v
  wire                  lri_srdy;               // From tc_ri of sd_input.v
  wire                  lro_drdy;               // From tc_ro of sd_output.v
  wire                  lro_srdy;               // From fsm of port_ring_tap_fsm.v
  // End of automatics
 
  /* sd_input AUTO_TEMPLATE "tc_\(.*\)"
   (
    .c_\(.*\)     (@_\1),
    .ip_\(.*\)    (l@_\1),
   );
   */
 
  sd_input #(rdp_sz) tc_ri
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (ri_drdy),               // Templated
     .ip_srdy                           (lri_srdy),              // Templated
     .ip_data                           (lri_data),              // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (ri_srdy),               // Templated
     .c_data                            (ri_data),               // Templated
     .ip_drdy                           (lri_drdy));             // Templated
 
  sd_input #(pdp_sz) tc_prx
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (prx_drdy),              // Templated
     .ip_srdy                           (lprx_srdy),             // Templated
     .ip_data                           (lprx_data),             // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (prx_srdy),              // Templated
     .c_data                            (prx_data),              // Templated
     .ip_drdy                           (lprx_drdy));            // Templated
 
  sd_input #(`NUM_PORTS) tc_fli
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (fli_drdy),              // Templated
     .ip_srdy                           (lfli_srdy),             // Templated
     .ip_data                           (lfli_data),             // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (fli_srdy),              // Templated
     .c_data                            (fli_data),              // Templated
     .ip_drdy                           (lfli_drdy));            // Templated
 
  port_ring_tap_fsm #(rdp_sz, pdp_sz, portnum) fsm
    (/*AUTOINST*/
     // Outputs
     .lfli_drdy                         (lfli_drdy),
     .lprx_drdy                         (lprx_drdy),
     .lptx_data                         (lptx_data[pdp_sz-1:0]),
     .lptx_srdy                         (lptx_srdy),
     .lri_drdy                          (lri_drdy),
     .lro_data                          (lro_data[rdp_sz-1:0]),
     .lro_srdy                          (lro_srdy),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .lfli_data                         (lfli_data[`NUM_PORTS-1:0]),
     .lfli_srdy                         (lfli_srdy),
     .lprx_data                         (lprx_data[pdp_sz-1:0]),
     .lprx_srdy                         (lprx_srdy),
     .lptx_drdy                         (lptx_drdy),
     .lri_data                          (lri_data[rdp_sz-1:0]),
     .lri_srdy                          (lri_srdy),
     .lro_drdy                          (lro_drdy));
 
  /* sd_output AUTO_TEMPLATE "tc_\(.*\)"
   (
    .ic_\(.*\)    (l@_\1),
    .p_\(.*\)     (@_\1),
   );
   */
 
  sd_output #(pdp_sz) tc_ptx
    (/*AUTOINST*/
     // Outputs
     .ic_drdy                           (lptx_drdy),             // Templated
     .p_srdy                            (ptx_srdy),              // Templated
     .p_data                            (ptx_data),              // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .ic_srdy                           (lptx_srdy),             // Templated
     .ic_data                           (lptx_data),             // Templated
     .p_drdy                            (ptx_drdy));             // Templated
 
  sd_output #(rdp_sz) tc_ro
    (/*AUTOINST*/
     // Outputs
     .ic_drdy                           (lro_drdy),              // Templated
     .p_srdy                            (ro_srdy),               // Templated
     .p_data                            (ro_data),               // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .ic_srdy                           (lro_srdy),              // Templated
     .ic_data                           (lro_data),              // Templated
     .p_drdy                            (ro_drdy));              // Templated
 
endmodule // port_ring_tap
// Local Variables:
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
// End:  

Line No.	Rev	Author	Line
1	5	ghutchis	`// Inputs are ri (Ring In), ro (Ring Out),`
2			`// fli (FIB lookup in), prx (port in/RX), and ptx (port out/TX)`
3
4			`module port_ring_tap`
5	8	ghutchis	#(parameter rdp_sz = `PRW_SZ,
6			parameter pdp_sz = `PFW_SZ,
7	5	ghutchis	`parameter portnum = 0)`
8			`(`
9			`input clk,`
10			`input reset,`
11
12			`input ri_srdy,`
13			`output ri_drdy,`
14			`input [rdp_sz-1:0] ri_data,`
15
16			`input prx_srdy,`
17			`output prx_drdy,`
18	8	ghutchis	`input [pdp_sz-1:0] prx_data,`
19	5	ghutchis
20			`output ro_srdy,`
21			`input ro_drdy,`
22			`output [rdp_sz-1:0] ro_data,`
23
24			`output ptx_srdy,`
25			`input ptx_drdy,`
26	8	ghutchis	`output [pdp_sz-1:0] ptx_data,`
27	5	ghutchis
28			`input fli_srdy,`
29			`output fli_drdy,`
30			input [`NUM_PORTS-1:0] fli_data
31			`);`
32
33	8	ghutchis	wire [`PRW_SZ-1:0] lri_data; // From tc_ri of sd_input.v
34			wire [`NUM_PORTS-1:0] lfli_data; // From tc_fli of sd_input.v
35			wire [`PFW_SZ-1:0] lprx_data; // From tc_prx of sd_input.v
36			wire [`PFW_SZ-1:0] lptx_data; // From fsm of port_ring_tap_fsm.v
37			wire [`PRW_SZ-1:0] lro_data; // From fsm of port_ring_tap_fsm.v
38	5	ghutchis	`/AUTOWIRE/`
39	8	ghutchis	`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
40			`wire lfli_drdy; // From fsm of port_ring_tap_fsm.v`
41			`wire lfli_srdy; // From tc_fli of sd_input.v`
42			`wire lprx_drdy; // From fsm of port_ring_tap_fsm.v`
43			`wire lprx_srdy; // From tc_prx of sd_input.v`
44			`wire lptx_drdy; // From tc_ptx of sd_output.v`
45			`wire lptx_srdy; // From fsm of port_ring_tap_fsm.v`
46			`wire lri_drdy; // From fsm of port_ring_tap_fsm.v`
47			`wire lri_srdy; // From tc_ri of sd_input.v`
48			`wire lro_drdy; // From tc_ro of sd_output.v`
49			`wire lro_srdy; // From fsm of port_ring_tap_fsm.v`
50			`// End of automatics`
51	5	ghutchis
52			`/* sd_input AUTO_TEMPLATE "tc_\(.*\)"`
53			`(`
54	8	ghutchis	`.c_\(.*\) (@_\1),`
55			`.ip_\(.*\) (l@_\1),`
56	5	ghutchis	`);`
57			`*/`
58
59			`sd_input #(rdp_sz) tc_ri`
60			`(/AUTOINST/`
61			`// Outputs`
62	8	ghutchis	`.c_drdy (ri_drdy), // Templated`
63			`.ip_srdy (lri_srdy), // Templated`
64			`.ip_data (lri_data), // Templated`
65	5	ghutchis	`// Inputs`
66	8	ghutchis	`.clk (clk),`
67			`.reset (reset),`
68			`.c_srdy (ri_srdy), // Templated`
69			`.c_data (ri_data), // Templated`
70			`.ip_drdy (lri_drdy)); // Templated`
71	5	ghutchis
72	8	ghutchis	`sd_input #(pdp_sz) tc_prx`
73	5	ghutchis	`(/AUTOINST/`
74			`// Outputs`
75	8	ghutchis	`.c_drdy (prx_drdy), // Templated`
76			`.ip_srdy (lprx_srdy), // Templated`
77			`.ip_data (lprx_data), // Templated`
78	5	ghutchis	`// Inputs`
79	8	ghutchis	`.clk (clk),`
80			`.reset (reset),`
81			`.c_srdy (prx_srdy), // Templated`
82			`.c_data (prx_data), // Templated`
83			`.ip_drdy (lprx_drdy)); // Templated`
84	5	ghutchis
85			sd_input #(`NUM_PORTS) tc_fli
86			`(/AUTOINST/`
87			`// Outputs`
88	8	ghutchis	`.c_drdy (fli_drdy), // Templated`
89			`.ip_srdy (lfli_srdy), // Templated`
90			`.ip_data (lfli_data), // Templated`
91	5	ghutchis	`// Inputs`
92	8	ghutchis	`.clk (clk),`
93			`.reset (reset),`
94			`.c_srdy (fli_srdy), // Templated`
95			`.c_data (fli_data), // Templated`
96			`.ip_drdy (lfli_drdy)); // Templated`
97	5	ghutchis
98	8	ghutchis	`port_ring_tap_fsm #(rdp_sz, pdp_sz, portnum) fsm`
99			`(/AUTOINST/`
100			`// Outputs`
101			`.lfli_drdy (lfli_drdy),`
102			`.lprx_drdy (lprx_drdy),`
103			`.lptx_data (lptx_data[pdp_sz-1:0]),`
104			`.lptx_srdy (lptx_srdy),`
105			`.lri_drdy (lri_drdy),`
106			`.lro_data (lro_data[rdp_sz-1:0]),`
107			`.lro_srdy (lro_srdy),`
108			`// Inputs`
109			`.clk (clk),`
110			`.reset (reset),`
111			.lfli_data (lfli_data[`NUM_PORTS-1:0]),
112			`.lfli_srdy (lfli_srdy),`
113			`.lprx_data (lprx_data[pdp_sz-1:0]),`
114			`.lprx_srdy (lprx_srdy),`
115			`.lptx_drdy (lptx_drdy),`
116			`.lri_data (lri_data[rdp_sz-1:0]),`
117			`.lri_srdy (lri_srdy),`
118			`.lro_drdy (lro_drdy));`
119
120	5	ghutchis	`/* sd_output AUTO_TEMPLATE "tc_\(.*\)"`
121			`(`
122	8	ghutchis	`.ic_\(.*\) (l@_\1),`
123			`.p_\(.*\) (@_\1),`
124	5	ghutchis	`);`
125			`*/`
126
127	8	ghutchis	`sd_output #(pdp_sz) tc_ptx`
128	5	ghutchis	`(/AUTOINST/`
129			`// Outputs`
130	8	ghutchis	`.ic_drdy (lptx_drdy), // Templated`
131			`.p_srdy (ptx_srdy), // Templated`
132			`.p_data (ptx_data), // Templated`
133	5	ghutchis	`// Inputs`
134	8	ghutchis	`.clk (clk),`
135			`.reset (reset),`
136			`.ic_srdy (lptx_srdy), // Templated`
137			`.ic_data (lptx_data), // Templated`
138			`.p_drdy (ptx_drdy)); // Templated`
139	5	ghutchis
140			`sd_output #(rdp_sz) tc_ro`
141			`(/AUTOINST/`
142			`// Outputs`
143	8	ghutchis	`.ic_drdy (lro_drdy), // Templated`
144			`.p_srdy (ro_srdy), // Templated`
145			`.p_data (ro_data), // Templated`
146	5	ghutchis	`// Inputs`
147	8	ghutchis	`.clk (clk),`
148			`.reset (reset),`
149			`.ic_srdy (lro_srdy), // Templated`
150			`.ic_data (lro_data), // Templated`
151			`.p_drdy (ro_drdy)); // Templated`
152	5	ghutchis
153			`endmodule // port_ring_tap`
154			`// Local Variables:`
155			`// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")`
156			`// End:`

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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [port_ring_tap.v] - Blame information for rev 8