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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [port_ring_tap_fsm.v] - Blame information for rev 11

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module port_ring_tap_fsm
  #(parameter rdp_sz = 64,
    parameter pdp_sz = 64,
    parameter portnum = 0)
  (
   input               clk,
   input               reset,
 
   output reg               lfli_drdy,
   output reg               lprx_drdy,
   output reg[pdp_sz-1:0]    lptx_data,
   output reg               lptx_srdy,
   output reg               lri_drdy,
   output reg[rdp_sz-1:0]    lro_data,
   output reg               lro_srdy,
 
   input [`NUM_PORTS-1:0]   lfli_data,
   input               lfli_srdy,
   input [pdp_sz-1:0]   lprx_data,
   input               lprx_srdy,
   input               lptx_drdy,
   input [rdp_sz-1:0]   lri_data,
   input               lri_srdy,
   input               lro_drdy
   );
 
  reg [4:0]            state, nxt_state;
 
  wire [`NUM_PORTS-1:0] port_mask;
  //reg [`NUM_PORTS-1:0]  pe_vec, nxt_pe_vec;
  wire [`NUM_PORTS-1:0] nxt_pe_vec = lri_data[`PRW_DATA] & ~port_mask;
 
  assign port_mask = 1 << portnum;
 
  localparam s_idle = 0,
             s_rfwd = 1,
             s_rcopy = 2,
             s_rsink = 3,
             s_tdata = 4;
  localparam ns_idle = 1,
             ns_rfwd = 2,
             ns_rcopy = 4,
             ns_rsink = 8,
             ns_tdata = 16;
 
  always @*
    begin
      lro_data = lri_data;
      lptx_data = lri_data;
      lfli_drdy = 0;
      lprx_drdy = 0;
      lptx_srdy = 0;
      lri_drdy  = 0;
      lro_srdy  = 0;
 
      case (1'b1)
        state[s_idle] :
          begin
            if (lfli_srdy)
              begin
                if (lfli_data != 0)
                  begin
                    lro_data = 0;
                    lro_data[`PRW_PVEC] = 1;
                    lro_data[`PRW_DATA] = lfli_data;
                    if (lro_drdy)
                      begin
                        lfli_drdy = 1;
                        lro_srdy = 1;
                        nxt_state = ns_tdata;
                      end
                  end
                else
                  lfli_drdy = 1;
              end
            else if (lri_srdy)
              begin
                if (lri_data[`PRW_DATA] & port_mask)
                  begin
                    // packet is for our port
                    //nxt_pe_vec = lri_data[`PRW_DATA] & ~port_mask;
 
                    // if enable vector is not empty, send the
                    // vector to the next port
                    if ((nxt_pe_vec != 0) & lro_drdy)
                      begin
                        lro_data[`PRW_DATA] = nxt_pe_vec;
                        lro_data[`PRW_PVEC] = 1;
                        lro_srdy = 1;
                        lri_drdy = 1;
                        nxt_state = ns_rcopy;
                      end
                    else if (nxt_pe_vec == 0)
                      begin
                        lri_drdy = 1;
                        nxt_state = ns_rsink;
                      end // else: !if((nxt_pe_vec != 0) & lro_drdy)
                  end // if (lri_data[`PRW_DATA] & port_mask)
                else
                  // packet is not for our port, forward it on the
                  // ring
                  begin
                    if (lro_drdy)
                      begin
                        lri_drdy = 1;
                        lro_srdy = 1;
                        nxt_state = ns_rfwd;
                      end
                  end // else: !if(lri_data[`PRW_DATA] & port_mask)
              end // if (lri_srdy)
          end // case: state[s_idle]
 
        // transmit data from port on to the ring
        state[s_tdata] :
          begin
            lro_data = lprx_data;
            lro_data[`PRW_PVEC] = 0;
            if (lro_drdy & lprx_srdy)
              begin
                lprx_drdy = 1;
                lro_srdy  = 1;
                if ((lprx_data[`PRW_PCC] == `PCC_EOP) |
                    (lprx_data[`PRW_PCC] == `PCC_BADEOP))
                  nxt_state = ns_idle;
              end
          end // case: state[s_tdata]
 
        // data on ring is for our port as well as further ports
        // copy ring data to our TX buffer as well as on the ring
        state[s_rcopy] :
          begin
            lro_data = lri_data;
            lptx_data = lri_data[`PFW_SZ-1:0];
            if (lri_srdy & lro_drdy & lptx_drdy)
              begin
                lri_drdy = 1;
                lro_srdy = 1;
                lptx_srdy = 1;
                if ((lri_data[`PRW_PCC] == `PCC_EOP) |
                    (lri_data[`PRW_PCC] == `PCC_BADEOP))
                  nxt_state = ns_idle;
              end
          end
 
        // data on ring is not for our port, copy from ring in to ring out
        state[s_rfwd] :
          begin
            lro_data = lri_data;
            if (lri_srdy & lro_drdy)
              begin
                lri_drdy = 1;
                lro_srdy = 1;
                if ((lri_data[`PRW_PCC] == `PCC_EOP) |
                    (lri_data[`PRW_PCC] == `PCC_BADEOP))
                  nxt_state = ns_idle;
              end
          end
 
        // data on ring is for our port and we are the last port
        // copy ring data to our TX buffer but do not copy to ring
        state[s_rsink] :
          begin
            lptx_data = lri_data[`PFW_SZ-1:0];
            if (lri_srdy & lptx_drdy)
              begin
                lri_drdy = 1;
                lptx_srdy = 1;
                if ((lri_data[`PRW_PCC] == `PCC_EOP) |
                    (lri_data[`PRW_PCC] == `PCC_BADEOP))
                  nxt_state = ns_idle;
              end
          end
 
        default : nxt_state = ns_idle;
      endcase // case (1'b1)
    end // always @ *
 
  always @(posedge clk)
    begin
      if (reset)
        begin
          state <= #1 1;
          /*AUTORESET*/
        end
      else
        begin
          state <= #1 nxt_state;
        end
    end // always @ (posedge clk)
 
 
 
endmodule // port_ring_tap_fsm

Line No.	Rev	Author	Line
1	5	ghutchis	`module port_ring_tap_fsm`
2			`#(parameter rdp_sz = 64,`
3	8	ghutchis	`parameter pdp_sz = 64,`
4	5	ghutchis	`parameter portnum = 0)`
5			`(`
6			`input clk,`
7			`input reset,`
8
9			`output reg lfli_drdy,`
10			`output reg lprx_drdy,`
11	8	ghutchis	`output reg[pdp_sz-1:0] lptx_data,`
12	5	ghutchis	`output reg lptx_srdy,`
13			`output reg lri_drdy,`
14			`output reg[rdp_sz-1:0] lro_data,`
15			`output reg lro_srdy,`
16
17	8	ghutchis	input [`NUM_PORTS-1:0] lfli_data,
18	5	ghutchis	`input lfli_srdy,`
19	8	ghutchis	`input [pdp_sz-1:0] lprx_data,`
20	5	ghutchis	`input lprx_srdy,`
21			`input lptx_drdy,`
22			`input [rdp_sz-1:0] lri_data,`
23			`input lri_srdy,`
24			`input lro_drdy`
25			`);`
26
27	8	ghutchis	`reg [4:0] state, nxt_state;`
28	5	ghutchis
29			wire [`NUM_PORTS-1:0] port_mask;
30	11	ghutchis	//reg [`NUM_PORTS-1:0] pe_vec, nxt_pe_vec;
31			wire [`NUM_PORTS-1:0] nxt_pe_vec = lri_data[`PRW_DATA] & ~port_mask;
32	5	ghutchis
33			`assign port_mask = 1 << portnum;`
34
35	8	ghutchis	`localparam s_idle = 0,`
36			`s_rfwd = 1,`
37			`s_rcopy = 2,`
38			`s_rsink = 3,`
39			`s_tdata = 4;`
40			`localparam ns_idle = 1,`
41			`ns_rfwd = 2,`
42			`ns_rcopy = 4,`
43			`ns_rsink = 8,`
44			`ns_tdata = 16;`
45	5	ghutchis
46			`always @*`
47			`begin`
48			`lro_data = lri_data;`
49	8	ghutchis	`lptx_data = lri_data;`
50			`lfli_drdy = 0;`
51			`lprx_drdy = 0;`
52			`lptx_srdy = 0;`
53			`lri_drdy = 0;`
54			`lro_srdy = 0;`
55	5	ghutchis
56			`case (1'b1)`
57			`state[s_idle] :`
58			`begin`
59			`if (lfli_srdy)`
60			`begin`
61	8	ghutchis	`if (lfli_data != 0)`
62			`begin`
63			`lro_data = 0;`
64			lro_data[`PRW_PVEC] = 1;
65			lro_data[`PRW_DATA] = lfli_data;
66			`if (lro_drdy)`
67			`begin`
68			`lfli_drdy = 1;`
69			`lro_srdy = 1;`
70			`nxt_state = ns_tdata;`
71			`end`
72			`end`
73			`else`
74			`lfli_drdy = 1;`
75	5	ghutchis	`end`
76			`else if (lri_srdy)`
77			`begin`
78			if (lri_data[`PRW_DATA] & port_mask)
79			`begin`
80			`// packet is for our port`
81	11	ghutchis	//nxt_pe_vec = lri_data[`PRW_DATA] & ~port_mask;
82	5	ghutchis
83			`// if enable vector is not empty, send the`
84			`// vector to the next port`
85			`if ((nxt_pe_vec != 0) & lro_drdy)`
86			`begin`
87			lro_data[`PRW_DATA] = nxt_pe_vec;
88			lro_data[`PRW_PVEC] = 1;
89			`lro_srdy = 1;`
90			`lri_drdy = 1;`
91			`nxt_state = ns_rcopy;`
92			`end`
93	11	ghutchis	`else if (nxt_pe_vec == 0)`
94	5	ghutchis	`begin`
95			`lri_drdy = 1;`
96			`nxt_state = ns_rsink;`
97			`end // else: !if((nxt_pe_vec != 0) & lro_drdy)`
98			end // if (lri_data[`PRW_DATA] & port_mask)
99			`else`
100			`// packet is not for our port, forward it on the`
101			`// ring`
102			`begin`
103			`if (lro_drdy)`
104			`begin`
105			`lri_drdy = 1;`
106			`lro_srdy = 1;`
107			`nxt_state = ns_rfwd;`
108			`end`
109			end // else: !if(lri_data[`PRW_DATA] & port_mask)
110			`end // if (lri_srdy)`
111			`end // case: state[s_idle]`
112
113	8	ghutchis	`// transmit data from port on to the ring`
114			`state[s_tdata] :`
115			`begin`
116			`lro_data = lprx_data;`
117			lro_data[`PRW_PVEC] = 0;
118			`if (lro_drdy & lprx_srdy)`
119			`begin`
120			`lprx_drdy = 1;`
121			`lro_srdy = 1;`
122			if ((lprx_data[`PRW_PCC] == `PCC_EOP) \|
123			(lprx_data[`PRW_PCC] == `PCC_BADEOP))
124			`nxt_state = ns_idle;`
125			`end`
126			`end // case: state[s_tdata]`
127
128			`// data on ring is for our port as well as further ports`
129			`// copy ring data to our TX buffer as well as on the ring`
130			`state[s_rcopy] :`
131			`begin`
132			`lro_data = lri_data;`
133			lptx_data = lri_data[`PFW_SZ-1:0];
134			`if (lri_srdy & lro_drdy & lptx_drdy)`
135			`begin`
136			`lri_drdy = 1;`
137			`lro_srdy = 1;`
138			`lptx_srdy = 1;`
139			if ((lri_data[`PRW_PCC] == `PCC_EOP) \|
140			(lri_data[`PRW_PCC] == `PCC_BADEOP))
141			`nxt_state = ns_idle;`
142			`end`
143			`end`
144
145			`// data on ring is not for our port, copy from ring in to ring out`
146			`state[s_rfwd] :`
147			`begin`
148			`lro_data = lri_data;`
149			`if (lri_srdy & lro_drdy)`
150			`begin`
151			`lri_drdy = 1;`
152			`lro_srdy = 1;`
153			if ((lri_data[`PRW_PCC] == `PCC_EOP) \|
154			(lri_data[`PRW_PCC] == `PCC_BADEOP))
155			`nxt_state = ns_idle;`
156			`end`
157			`end`
158
159			`// data on ring is for our port and we are the last port`
160			`// copy ring data to our TX buffer but do not copy to ring`
161	11	ghutchis	`state[s_rsink] :`
162	8	ghutchis	`begin`
163			lptx_data = lri_data[`PFW_SZ-1:0];
164			`if (lri_srdy & lptx_drdy)`
165			`begin`
166			`lri_drdy = 1;`
167			`lptx_srdy = 1;`
168			if ((lri_data[`PRW_PCC] == `PCC_EOP) \|
169			(lri_data[`PRW_PCC] == `PCC_BADEOP))
170			`nxt_state = ns_idle;`
171			`end`
172			`end`
173
174	5	ghutchis	`default : nxt_state = ns_idle;`
175			`endcase // case (1'b1)`
176			`end // always @ *`
177	8	ghutchis
178			`always @(posedge clk)`
179			`begin`
180			`if (reset)`
181			`begin`
182			`state <= #1 1;`
183			`/AUTORESET/`
184			`end`
185			`else`
186			`begin`
187			`state <= #1 nxt_state;`
188			`end`
189			`end // always @ (posedge clk)`
190
191	5	ghutchis
192
193			`endmodule // port_ring_tap_fsm`

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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [port_ring_tap_fsm.v] - Blame information for rev 11