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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [port_ring_tap_fsm.v] - Blame information for rev 8

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1 5 ghutchis 
module port_ring_tap_fsm
2 
  #(parameter rdp_sz = 64,
3 8 ghutchis 
    parameter pdp_sz = 64,
4 5 ghutchis 
    parameter portnum = 0)
5 
  (
6 
   input               clk,
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   input               reset,
8 
 
9 
   output reg               lfli_drdy,
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   output reg               lprx_drdy,
11 8 ghutchis 
   output reg[pdp_sz-1:0]    lptx_data,
12 5 ghutchis 
   output reg               lptx_srdy,
13 
   output reg               lri_drdy,
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   output reg[rdp_sz-1:0]    lro_data,
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   output reg               lro_srdy,
16 
 
17 8 ghutchis 
   input [`NUM_PORTS-1:0]   lfli_data,
18 5 ghutchis 
   input               lfli_srdy,
19 8 ghutchis 
   input [pdp_sz-1:0]   lprx_data,
20 5 ghutchis 
   input               lprx_srdy,
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   input               lptx_drdy,
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   input [rdp_sz-1:0]   lri_data,
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   input               lri_srdy,
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   input               lro_drdy
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   );
26 
 
27 8 ghutchis 
  reg [4:0]            state, nxt_state;
28 5 ghutchis 
 
29 
  wire [`NUM_PORTS-1:0] port_mask;
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  reg [`NUM_PORTS-1:0]  pe_vec, nxt_pe_vec;
31 
 
32 
  assign port_mask = 1 << portnum;
33 
 
34 8 ghutchis 
  localparam s_idle = 0,
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             s_rfwd = 1,
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             s_rcopy = 2,
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             s_rsink = 3,
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             s_tdata = 4;
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  localparam ns_idle = 1,
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             ns_rfwd = 2,
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             ns_rcopy = 4,
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             ns_rsink = 8,
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             ns_tdata = 16;
44 5 ghutchis 
 
45 
  always @*
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    begin
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      lro_data = lri_data;
48 8 ghutchis 
      lptx_data = lri_data;
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      lfli_drdy = 0;
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      lprx_drdy = 0;
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      lptx_srdy = 0;
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      lri_drdy  = 0;
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      lro_srdy  = 0;
54 5 ghutchis 
 
55 
      case (1'b1)
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        state[s_idle] :
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          begin
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            if (lfli_srdy)
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              begin
60 8 ghutchis 
                if (lfli_data != 0)
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                  begin
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                    lro_data = 0;
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                    lro_data[`PRW_PVEC] = 1;
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                    lro_data[`PRW_DATA] = lfli_data;
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                    if (lro_drdy)
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                      begin
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                        lfli_drdy = 1;
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                        lro_srdy = 1;
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                        nxt_state = ns_tdata;
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                      end
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                  end
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                else
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                  lfli_drdy = 1;
74 5 ghutchis 
              end
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            else if (lri_srdy)
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              begin
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                if (lri_data[`PRW_DATA] & port_mask)
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                  begin
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                    // packet is for our port
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                    nxt_pe_vec = lri_data[`PRW_DATA] & ~port_mask;
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                    // if enable vector is not empty, send the
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                    // vector to the next port
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                    if ((nxt_pe_vec != 0) & lro_drdy)
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                      begin
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                        lro_data[`PRW_DATA] = nxt_pe_vec;
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                        lro_data[`PRW_PVEC] = 1;
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                        lro_srdy = 1;
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                        lri_drdy = 1;
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                        nxt_state = ns_rcopy;
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                      end
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                    else
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                      begin
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                        lri_drdy = 1;
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                        nxt_state = ns_rsink;
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                      end // else: !if((nxt_pe_vec != 0) & lro_drdy)
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                  end // if (lri_data[`PRW_DATA] & port_mask)
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                else
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                  // packet is not for our port, forward it on the
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                  // ring
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                  begin
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                    if (lro_drdy)
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                      begin
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                        lri_drdy = 1;
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                        lro_srdy = 1;
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                        nxt_state = ns_rfwd;
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                      end
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                  end // else: !if(lri_data[`PRW_DATA] & port_mask)
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              end // if (lri_srdy)
110 
          end // case: state[s_idle]
111 
 
112 8 ghutchis 
        // transmit data from port on to the ring
113 
        state[s_tdata] :
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          begin
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            lro_data = lprx_data;
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            lro_data[`PRW_PVEC] = 0;
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            if (lro_drdy & lprx_srdy)
118 
              begin
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                lprx_drdy = 1;
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                lro_srdy  = 1;
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                if ((lprx_data[`PRW_PCC] == `PCC_EOP) |
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                    (lprx_data[`PRW_PCC] == `PCC_BADEOP))
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                  nxt_state = ns_idle;
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              end
125 
          end // case: state[s_tdata]
126 
 
127 
        // data on ring is for our port as well as further ports
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        // copy ring data to our TX buffer as well as on the ring
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        state[s_rcopy] :
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          begin
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            lro_data = lri_data;
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            lptx_data = lri_data[`PFW_SZ-1:0];
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            if (lri_srdy & lro_drdy & lptx_drdy)
134 
              begin
135 
                lri_drdy = 1;
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                lro_srdy = 1;
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                lptx_srdy = 1;
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                if ((lri_data[`PRW_PCC] == `PCC_EOP) |
139 
                    (lri_data[`PRW_PCC] == `PCC_BADEOP))
140 
                  nxt_state = ns_idle;
141 
              end
142 
          end
143 
 
144 
        // data on ring is not for our port, copy from ring in to ring out
145 
        state[s_rfwd] :
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          begin
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            lro_data = lri_data;
148 
            if (lri_srdy & lro_drdy)
149 
              begin
150 
                lri_drdy = 1;
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                lro_srdy = 1;
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                if ((lri_data[`PRW_PCC] == `PCC_EOP) |
153 
                    (lri_data[`PRW_PCC] == `PCC_BADEOP))
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                  nxt_state = ns_idle;
155 
              end
156 
          end
157 
 
158 
        // data on ring is for our port and we are the last port
159 
        // copy ring data to our TX buffer but do not copy to ring
160 
        state[s_rcopy] :
161 
          begin
162 
            lptx_data = lri_data[`PFW_SZ-1:0];
163 
            if (lri_srdy & lptx_drdy)
164 
              begin
165 
                lri_drdy = 1;
166 
                lptx_srdy = 1;
167 
                if ((lri_data[`PRW_PCC] == `PCC_EOP) |
168 
                    (lri_data[`PRW_PCC] == `PCC_BADEOP))
169 
                  nxt_state = ns_idle;
170 
              end
171 
          end
172 
 
173 5 ghutchis 
        default : nxt_state = ns_idle;
174 
      endcase // case (1'b1)
175 
    end // always @ *
176 8 ghutchis 
 
177 
  always @(posedge clk)
178 
    begin
179 
      if (reset)
180 
        begin
181 
          state <= #1 1;
182 
          /*AUTORESET*/
183 
        end
184 
      else
185 
        begin
186 
          state <= #1 nxt_state;
187 
        end
188 
    end // always @ (posedge clk)
189 
 
190 5 ghutchis 
 
191 
 
192 
endmodule // port_ring_tap_fsm

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