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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [sd_tx_gigmac.v] - Blame information for rev 14

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Line No. Rev Author Line
1 8 ghutchis
// mock-up of RX portion of gigabit ethernet MAC
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// performs packet reception and creates internal
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// packet codes, as well as checking CRC on incoming
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// packets.
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// If output is not ready while receiving data,
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// truncates the packet and makes it an error packet.
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module sd_tx_gigmac
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  (
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   input        clk,
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   input        reset,
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   output reg        gmii_tx_en,
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   output reg [7:0]  gmii_txd,
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   input       txg_srdy,
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   output      txg_drdy,
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   input [1:0] txg_code,
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   input [7:0] txg_data
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   );
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  wire         ip_srdy;
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  reg          ip_drdy;
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  wire [1:0]   ip_code;
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  wire [7:0]   ip_data;
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  reg [3:0]    count, nxt_count;
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  reg [7:0]    nxt_gmii_txd;
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  reg          nxt_gmii_tx_en;
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  reg [3:0]    state, nxt_state;
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  localparam s_idle = 0, s_preamble = 1, s_payload = 2, s_ipg = 3;
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  localparam ns_idle = 1, ns_preamble = 2, ns_payload = 4, ns_ipg = 8;
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  sd_input #(8+2) in_hold
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    (
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     // Outputs
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     .c_drdy                            (txg_drdy),
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     .ip_srdy                           (ip_srdy),
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     .ip_data                           ({ip_code,ip_data}),
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     // Inputs
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     .clk                               (clk),
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     .reset                             (reset),
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     .c_srdy                            (txg_srdy),
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     .c_data                            ({txg_code,txg_data}),
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     .ip_drdy                           (ip_drdy));
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  always @*
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    begin
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      ip_drdy = 0;
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      nxt_count = count;
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      nxt_gmii_tx_en = 0;
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      nxt_gmii_txd = gmii_txd;
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      case (1'b1)
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        state[s_idle] :
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          begin
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            if (ip_srdy & (ip_code == `PCC_SOP))
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              begin
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                nxt_gmii_tx_en = 1;
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                nxt_gmii_txd = `GMII_PRE;
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                nxt_count = 1;
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                nxt_state = ns_preamble;
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              end
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            else
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              begin
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                ip_drdy = 1;
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              end // else: !if(ip_srdy & (ip_code == `PCC_SOP))
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          end // case: state[s_idle]
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        state[s_preamble] :
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          begin
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            nxt_count = count + 1;
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            nxt_gmii_tx_en = 1;
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            if (count == 6)
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              begin
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                nxt_gmii_txd = `GMII_SFD;
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                nxt_state = ns_payload;
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              end
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            else
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              nxt_gmii_txd = `GMII_PRE;
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          end // case: state[s_preamble]
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        state[s_payload] :
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          begin
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            ip_drdy = 1;
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            nxt_gmii_tx_en = 1;
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            nxt_gmii_txd = ip_data;
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            if (!ip_srdy | ((ip_code == `PCC_EOP) | (ip_code == `PCC_BADEOP)))
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              begin
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                nxt_count = 0;
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                nxt_state = ns_ipg;
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              end
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          end // case: state[s_payload]
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        state[s_ipg] :
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          begin
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            nxt_gmii_tx_en = 0;
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            ip_drdy = 0;
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            nxt_count = count + 1;
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            if (count == 11)
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              nxt_state = ns_idle;
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          end
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        default : nxt_state = ns_idle;
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      endcase // case (1'b1)
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    end // always @ *
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  always @(posedge clk)
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    begin
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      if (reset)
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        begin
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          state <= #1 1;
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          /*AUTORESET*/
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          // Beginning of autoreset for uninitialized flops
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          count <= 4'h0;
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          gmii_tx_en <= 1'h0;
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          gmii_txd <= 8'h0;
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          // End of automatics
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        end
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      else
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        begin
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          state <= #1 nxt_state;
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          count <= #1 nxt_count;
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          gmii_tx_en <= #1 nxt_gmii_tx_en;
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          gmii_txd   <= #1 nxt_gmii_txd;
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        end // else: !if(reset)
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    end // always @ (posedge clk)
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endmodule // sd_rx_gigmac
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// Local Variables:
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// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
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// End:  

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