URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [sd_tx_gigmac.v] - Blame information for rev 8

Go to most recent revision | Details | Compare with Previous | View Log


// mock-up of RX portion of gigabit ethernet MAC
// performs packet reception and creates internal
// packet codes, as well as checking CRC on incoming
// packets.
 
// If output is not ready while receiving data,
// truncates the packet and makes it an error packet.
 
module sd_tx_gigmac
  (
   input        clk,
   input        reset,
   output reg        gmii_tx_dv,
   output reg [7:0]  gmii_txd,
 
   input       txg_srdy,
   output      txg_drdy,
   input [1:0] txg_code,
   input [7:0] txg_data
   );
 
  wire         ip_srdy;
  reg          ip_drdy;
  wire [1:0]   ip_code;
  wire [7:0]   ip_data;
  reg [3:0]    count, nxt_count;
 
  reg [7:0]    nxt_gmii_txd;
  reg          nxt_gmii_tx_dv;
  reg [3:0]    state, nxt_state;
 
  localparam s_idle = 0, s_preamble = 1, s_payload = 2, s_ipg = 3;
  localparam ns_idle = 1, ns_preamble = 2, ns_payload = 4, ns_ipg = 8;
 
  sd_input #(8+2) in_hold
    (
     // Outputs
     .c_drdy                            (txg_drdy),
     .ip_srdy                           (ip_srdy),
     .ip_data                           ({ip_code,ip_data}),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (txg_srdy),
     .c_data                            ({txg_code,txg_data}),
     .ip_drdy                           (ip_drdy));
 
  always @*
    begin
      ip_drdy = 0;
      nxt_count = count;
      nxt_gmii_tx_dv = 0;
      nxt_gmii_txd = gmii_txd;
 
      case (1'b1)
        state[s_idle] :
          begin
            if (ip_srdy & (ip_code == `PCC_SOP))
              begin
                nxt_gmii_tx_dv = 1;
                nxt_gmii_txd = `GMII_PRE;
                nxt_count = 1;
                nxt_state = ns_preamble;
              end
            else
              begin
                ip_drdy = 1;
              end // else: !if(ip_srdy & (ip_code == `PCC_SOP))
          end // case: state[s_idle]
 
        state[s_preamble] :
          begin
            nxt_count = count + 1;
            nxt_gmii_tx_dv = 1;
            if (count == 6)
              nxt_gmii_txd = `GMII_SFD;
            else
              nxt_gmii_txd = `GMII_PRE;
 
            if (count == 7)
              nxt_state = ns_payload;
          end // case: state[s_preamble]
 
        state[s_payload] :
          begin
            ip_drdy = 1;
 
            if (!ip_srdy | ((ip_code == `PCC_EOP) | (ip_code == `PCC_BADEOP)))
              begin
                nxt_gmii_tx_dv = 0;
                nxt_count = 0;
                nxt_state = ns_ipg;
              end
          end // case: state[s_payload]
 
        state[s_ipg] :
          begin
            nxt_gmii_tx_dv = 0;
            ip_drdy = 0;
            nxt_count = count + 1;
            if (count == 11)
              nxt_state = ns_idle;
          end
 
        default : nxt_state = ns_idle;
      endcase // case (1'b1)
    end // always @ *
 
  always @(posedge clk)
    begin
      if (reset)
        begin
          state <= #1 1;
          /*AUTORESET*/
          // Beginning of autoreset for uninitialized flops
          count <= 4'h0;
          gmii_tx_dv <= 1'h0;
          gmii_txd <= 8'h0;
          // End of automatics
        end
      else
        begin
          state <= #1 nxt_state;
          count <= #1 nxt_count;
          gmii_tx_dv <= #1 nxt_gmii_tx_dv;
          gmii_txd   <= #1 nxt_gmii_txd;
        end // else: !if(reset)
    end // always @ (posedge clk)
 
endmodule // sd_rx_gigmac
// Local Variables:
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
// End:  

Line No.	Rev	Author	Line
1	8	ghutchis	`// mock-up of RX portion of gigabit ethernet MAC`
2			`// performs packet reception and creates internal`
3			`// packet codes, as well as checking CRC on incoming`
4			`// packets.`
5
6			`// If output is not ready while receiving data,`
7			`// truncates the packet and makes it an error packet.`
8
9			`module sd_tx_gigmac`
10			`(`
11			`input clk,`
12			`input reset,`
13			`output reg gmii_tx_dv,`
14			`output reg [7:0] gmii_txd,`
15
16			`input txg_srdy,`
17			`output txg_drdy,`
18			`input [1:0] txg_code,`
19			`input [7:0] txg_data`
20			`);`
21
22			`wire ip_srdy;`
23			`reg ip_drdy;`
24			`wire [1:0] ip_code;`
25			`wire [7:0] ip_data;`
26			`reg [3:0] count, nxt_count;`
27
28			`reg [7:0] nxt_gmii_txd;`
29			`reg nxt_gmii_tx_dv;`
30			`reg [3:0] state, nxt_state;`
31
32			`localparam s_idle = 0, s_preamble = 1, s_payload = 2, s_ipg = 3;`
33			`localparam ns_idle = 1, ns_preamble = 2, ns_payload = 4, ns_ipg = 8;`
34
35			`sd_input #(8+2) in_hold`
36			`(`
37			`// Outputs`
38			`.c_drdy (txg_drdy),`
39			`.ip_srdy (ip_srdy),`
40			`.ip_data ({ip_code,ip_data}),`
41			`// Inputs`
42			`.clk (clk),`
43			`.reset (reset),`
44			`.c_srdy (txg_srdy),`
45			`.c_data ({txg_code,txg_data}),`
46			`.ip_drdy (ip_drdy));`
47
48			`always @*`
49			`begin`
50			`ip_drdy = 0;`
51			`nxt_count = count;`
52			`nxt_gmii_tx_dv = 0;`
53			`nxt_gmii_txd = gmii_txd;`
54
55			`case (1'b1)`
56			`state[s_idle] :`
57			`begin`
58			if (ip_srdy & (ip_code == `PCC_SOP))
59			`begin`
60			`nxt_gmii_tx_dv = 1;`
61			nxt_gmii_txd = `GMII_PRE;
62			`nxt_count = 1;`
63			`nxt_state = ns_preamble;`
64			`end`
65			`else`
66			`begin`
67			`ip_drdy = 1;`
68			end // else: !if(ip_srdy & (ip_code == `PCC_SOP))
69			`end // case: state[s_idle]`
70
71			`state[s_preamble] :`
72			`begin`
73			`nxt_count = count + 1;`
74			`nxt_gmii_tx_dv = 1;`
75			`if (count == 6)`
76			nxt_gmii_txd = `GMII_SFD;
77			`else`
78			nxt_gmii_txd = `GMII_PRE;
79
80			`if (count == 7)`
81			`nxt_state = ns_payload;`
82			`end // case: state[s_preamble]`
83
84			`state[s_payload] :`
85			`begin`
86			`ip_drdy = 1;`
87
88			if (!ip_srdy \| ((ip_code == `PCC_EOP) \| (ip_code == `PCC_BADEOP)))
89			`begin`
90			`nxt_gmii_tx_dv = 0;`
91			`nxt_count = 0;`
92			`nxt_state = ns_ipg;`
93			`end`
94			`end // case: state[s_payload]`
95
96			`state[s_ipg] :`
97			`begin`
98			`nxt_gmii_tx_dv = 0;`
99			`ip_drdy = 0;`
100			`nxt_count = count + 1;`
101			`if (count == 11)`
102			`nxt_state = ns_idle;`
103			`end`
104
105			`default : nxt_state = ns_idle;`
106			`endcase // case (1'b1)`
107			`end // always @ *`
108
109			`always @(posedge clk)`
110			`begin`
111			`if (reset)`
112			`begin`
113			`state <= #1 1;`
114			`/AUTORESET/`
115			`// Beginning of autoreset for uninitialized flops`
116			`count <= 4'h0;`
117			`gmii_tx_dv <= 1'h0;`
118			`gmii_txd <= 8'h0;`
119			`// End of automatics`
120			`end`
121			`else`
122			`begin`
123			`state <= #1 nxt_state;`
124			`count <= #1 nxt_count;`
125			`gmii_tx_dv <= #1 nxt_gmii_tx_dv;`
126			`gmii_txd <= #1 nxt_gmii_txd;`
127			`end // else: !if(reset)`
128			`end // always @ (posedge clk)`
129
130			`endmodule // sd_rx_gigmac`
131			`// Local Variables:`
132			`// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")`
133			`// End:`

Browse

Tools

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [sd_tx_gigmac.v] - Blame information for rev 8