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//////////////////////////////////////////////////////////////////////
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//// ////
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//// MAC_rx.v ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// ////
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//// Author(s): ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: MAC_rx.v,v $
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// Revision 1.3 2006/01/19 14:07:52 maverickist
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// verification is complete.
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//
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// Revision 1.2 2005/12/16 06:44:13 Administrator
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// replaced tab with space.
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// passed 9.6k length frame test.
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//
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// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
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// no message
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//
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module MAC_rx (
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input Reset ,
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input Clk_user,
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input Clk ,
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//RMII interface
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input MCrs_dv ,
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input [7:0] MRxD ,
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input MRxErr ,
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//flow_control signals
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output [15:0] pause_quanta ,
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output pause_quanta_val ,
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//user interface
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output Rx_mac_ra ,
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input Rx_mac_rd ,
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output [31:0] Rx_mac_data ,
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output [1:0] Rx_mac_BE ,
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output Rx_mac_pa ,
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output Rx_mac_sop ,
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output Rx_mac_eop ,
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//CPU
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input MAC_rx_add_chk_en ,
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input [7:0] MAC_add_prom_data ,
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input [2:0] MAC_add_prom_add ,
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input MAC_add_prom_wr ,
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input broadcast_filter_en ,
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input [15:0] broadcast_bucket_depth ,
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input [15:0] broadcast_bucket_interval ,
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input RX_APPEND_CRC,
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input [4:0] Rx_Hwmark ,
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input [4:0] Rx_Lwmark ,
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input CRC_chk_en ,
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input [5:0] RX_IFG_SET ,
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input [15:0] RX_MAX_LENGTH ,// 1518
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input [6:0] RX_MIN_LENGTH ,// 64
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//RMON interface
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output [15:0] Rx_pkt_length_rmon ,
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output Rx_apply_rmon ,
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output [2:0] Rx_pkt_err_type_rmon ,
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output [2:0] Rx_pkt_type_rmon
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);
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//******************************************************************************
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//internal signals
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//******************************************************************************
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//CRC_chk interface
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wire CRC_en ;
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wire CRC_init;
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wire CRC_err ;
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//MAC_rx_add_chk interface
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wire MAC_add_en ;
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wire MAC_rx_add_chk_err ;
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//broadcast_filter
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wire broadcast_ptr ;
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wire broadcast_drop ;
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//flow_control signals
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//wire [15:0] pause_quanta ;
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//wire pause_quanta_val ;
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//MAC_rx_ctrl interface
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wire [7:0] Fifo_data ;
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wire Fifo_data_en ;
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wire Fifo_full ;
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wire Fifo_data_err ;
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wire Fifo_data_end ;
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//******************************************************************************
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//instantiation
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//******************************************************************************
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MAC_rx_ctrl U_MAC_rx_ctrl(
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.Reset (Reset ),
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.Clk (Clk ),
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//RMII interface ( //RMII interface ),
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.MCrs_dv (MCrs_dv ),
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.MRxD (MRxD ),
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.MRxErr (MRxErr ),
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//CRC_chk interface (//CRC_chk interface ),
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.CRC_en (CRC_en ),
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.CRC_init (CRC_init ),
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.CRC_err (CRC_err ),
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//MAC_rx_add_chk interface (//MAC_rx_add_chk interface),
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.MAC_add_en (MAC_add_en ),
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.MAC_rx_add_chk_err (MAC_rx_add_chk_err ),
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//broadcast_filter (//broadcast_filter ),
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.broadcast_ptr (broadcast_ptr ),
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.broadcast_drop (broadcast_drop ),
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//flow_control signals (//flow_control signals ),
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.pause_quanta (pause_quanta ),
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.pause_quanta_val (pause_quanta_val ),
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//MAC_rx_FF interface (//MAC_rx_FF interface ),
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.Fifo_data (Fifo_data ),
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.Fifo_data_en (Fifo_data_en ),
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.Fifo_data_err (Fifo_data_err ),
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.Fifo_data_end (Fifo_data_end ),
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.Fifo_full (Fifo_full ),
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//RMON interface (//RMON interface ),
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.Rx_pkt_type_rmon (Rx_pkt_type_rmon ),
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.Rx_pkt_length_rmon (Rx_pkt_length_rmon ),
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.Rx_apply_rmon (Rx_apply_rmon ),
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.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ),
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//CPU (//CPU ),
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.RX_IFG_SET (RX_IFG_SET ),
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.RX_MAX_LENGTH (RX_MAX_LENGTH ),
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.RX_MIN_LENGTH (RX_MIN_LENGTH )
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);
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MAC_rx_FF U_MAC_rx_FF (
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.Reset (Reset ),
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.Clk_MAC (Clk ),
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.Clk_SYS (Clk_user ),
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//MAC_rx_ctrl interface (//MAC_rx_ctrl interface ),
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.Fifo_data (Fifo_data ),
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.Fifo_data_en (Fifo_data_en ),
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.Fifo_full (Fifo_full ),
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.Fifo_data_err (Fifo_data_err ),
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.Fifo_data_end (Fifo_data_end ),
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//CPU (//CPU ),
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.Rx_Hwmark (Rx_Hwmark ),
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.Rx_Lwmark (Rx_Lwmark ),
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.RX_APPEND_CRC (RX_APPEND_CRC ),
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//user interface (//user interface ),
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.Rx_mac_ra (Rx_mac_ra ),
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.Rx_mac_rd (Rx_mac_rd ),
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.Rx_mac_data (Rx_mac_data ),
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.Rx_mac_BE (Rx_mac_BE ),
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.Rx_mac_sop (Rx_mac_sop ),
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.Rx_mac_pa (Rx_mac_pa ),
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.Rx_mac_eop (Rx_mac_eop )
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);
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`ifdef MAC_BROADCAST_FILTER_EN
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Broadcast_filter U_Broadcast_filter(
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.Reset (Reset ),
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.Clk (Clk ),
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//MAC_rx_ctrl (//MAC_rx_ctrl ),
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.broadcast_ptr (broadcast_ptr ),
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.broadcast_drop (broadcast_drop ),
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//FromCPU (//FromCPU ),
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.broadcast_filter_en (broadcast_filter_en ),
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.broadcast_bucket_depth (broadcast_bucket_depth ),
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.broadcast_bucket_interval (broadcast_bucket_interval )
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);
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`else
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assign broadcast_drop=0;
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`endif
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CRC_chk U_CRC_chk(
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.Reset (Reset ),
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.Clk (Clk ),
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.CRC_data (Fifo_data ),
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.CRC_init (CRC_init ),
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.CRC_en (CRC_en ),
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//From CPU (//From CPU ),
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.CRC_chk_en (CRC_chk_en ),
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.CRC_err (CRC_err )
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);
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`ifdef MAC_TARGET_CHECK_EN
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MAC_rx_add_chk U_MAC_rx_add_chk(
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.Reset (Reset ),
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.Clk (Clk ),
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.Init (CRC_init ),
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.data (Fifo_data ),
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.MAC_add_en (MAC_add_en ),
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.MAC_rx_add_chk_err (MAC_rx_add_chk_err ),
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//From CPU (//From CPU ),
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.MAC_rx_add_chk_en (MAC_rx_add_chk_en ),
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.MAC_add_prom_data (MAC_add_prom_data ),
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.MAC_add_prom_add (MAC_add_prom_add ),
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.MAC_add_prom_wr (MAC_add_prom_wr )
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);
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`else
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assign MAC_rx_add_chk_err=0;
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`endif
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endmodule
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