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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [buffers/] [sd_fifo_head_b.v] - Blame information for rev 2

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//----------------------------------------------------------------------
// Srdy/Drdy FIFO Head "B"
//
// Building block for FIFOs.  The "B" (big) FIFO is design for larger FIFOs
// based around memories, with sizes that may not be a power of 2.
//
// The bound inputs allow multiple FIFO controllers to share a single
// memory.  The enable input is for arbitration between multiple FIFO
// controllers, or between the fifo head and tail controllers on a
// single port memory.
//
// The commit parameter enables write/commit behavior.  This creates
// two write pointers, one which is used for writing to memory and
// a commit pointer which is sent to the tail block.
//
// Naming convention: c = consumer, p = producer, i = internal interface
//----------------------------------------------------------------------
// Author: Guy Hutchison
//
// This block is uncopyrighted and released into the public domain.
//----------------------------------------------------------------------
 
// delay unit for nonblocking assigns, default is to #1
`ifndef SDLIB_DELAY
 `define SDLIB_DELAY #1
`endif
 
module sd_fifo_head_b
  #(parameter depth=16,
    parameter commit=0,
    parameter asz=$clog2(depth)
  )
  (
   input       clk,
   input       reset,
   input       enable,
   input       c_commit,
   input       c_abort,  // should be asserted when c_srdy == 0
   input       c_srdy,
   output      c_drdy,
 
   input [asz-1:0]  bound_low,
   input [asz-1:0]  bound_high,
 
   input [asz-1:0]      rdptr,
   output reg [asz-1:0] cur_wrptr,
   output reg [asz-1:0] com_wrptr,
   output reg         mem_we
   );
 
  reg [asz-1:0]       nxt_wrptr;
  reg [asz-1:0]       wrptr_p1;
  reg                   empty;
  reg                   full, nxt_full;
  reg [asz-1:0]         nxt_com_wrptr;
  generate if (!commit)
    always @* com_wrptr = cur_wrptr;
  endgenerate
 
  assign                c_drdy = !full & enable;
 
  always @*
    begin
      if (cur_wrptr[asz-1:0] == bound_high)
        begin
          wrptr_p1[asz-1:0] = bound_low;
        end
      else
        wrptr_p1 = cur_wrptr + 1;
 
      empty = (cur_wrptr == rdptr) & !full;
      nxt_full = (wrptr_p1 == rdptr);
 
      if ((commit == 1) && c_abort)
        begin
          nxt_wrptr = com_wrptr;
        end
      else if (enable & c_srdy & !full)
        begin
          nxt_wrptr = wrptr_p1;
          mem_we = 1;
        end
      else
        begin
          nxt_wrptr = cur_wrptr;
          mem_we = 0;
        end
    end
 
  always @(posedge clk)
    begin
      if (reset)
        begin
          cur_wrptr <= `SDLIB_DELAY bound_low;
          full  <= `SDLIB_DELAY 0;
        end
      else
        begin
          cur_wrptr <= `SDLIB_DELAY nxt_wrptr;
          full  <= `SDLIB_DELAY nxt_full;
        end // else: !if(reset)
    end // always @ (posedge clk)
 
  generate if (commit)
    always @*
      begin
        if (enable & c_commit & !c_abort & c_srdy & !full)
          nxt_com_wrptr = wrptr_p1;
        else
          nxt_com_wrptr = com_wrptr;
      end
 
    always @(posedge clk)
      begin
        if (reset)
          com_wrptr <= `SDLIB_DELAY bound_low;
        else
          com_wrptr <= `SDLIB_DELAY nxt_com_wrptr;
      end
  endgenerate
 
endmodule // fifo_head
 

Line No.	Rev	Author	Line
1	2	ghutchis	`//----------------------------------------------------------------------`
2			`// Srdy/Drdy FIFO Head "B"`
3			`//`
4			`// Building block for FIFOs. The "B" (big) FIFO is design for larger FIFOs`
5			`// based around memories, with sizes that may not be a power of 2.`
6			`//`
7			`// The bound inputs allow multiple FIFO controllers to share a single`
8			`// memory. The enable input is for arbitration between multiple FIFO`
9			`// controllers, or between the fifo head and tail controllers on a`
10			`// single port memory.`
11			`//`
12			`// The commit parameter enables write/commit behavior. This creates`
13			`// two write pointers, one which is used for writing to memory and`
14			`// a commit pointer which is sent to the tail block.`
15			`//`
16			`// Naming convention: c = consumer, p = producer, i = internal interface`
17			`//----------------------------------------------------------------------`
18			`// Author: Guy Hutchison`
19			`//`
20			`// This block is uncopyrighted and released into the public domain.`
21			`//----------------------------------------------------------------------`
22
23			`// delay unit for nonblocking assigns, default is to #1`
24			`ifndef SDLIB_DELAY
25			`define SDLIB_DELAY #1
26			`endif
27
28			`module sd_fifo_head_b`
29			`#(parameter depth=16,`
30			`parameter commit=0,`
31			`parameter asz=$clog2(depth)`
32			`)`
33			`(`
34			`input clk,`
35			`input reset,`
36			`input enable,`
37			`input c_commit,`
38			`input c_abort, // should be asserted when c_srdy == 0`
39			`input c_srdy,`
40			`output c_drdy,`
41
42			`input [asz-1:0] bound_low,`
43			`input [asz-1:0] bound_high,`
44
45			`input [asz-1:0] rdptr,`
46			`output reg [asz-1:0] cur_wrptr,`
47			`output reg [asz-1:0] com_wrptr,`
48			`output reg mem_we`
49			`);`
50
51			`reg [asz-1:0] nxt_wrptr;`
52			`reg [asz-1:0] wrptr_p1;`
53			`reg empty;`
54			`reg full, nxt_full;`
55			`reg [asz-1:0] nxt_com_wrptr;`
56			`generate if (!commit)`
57			`always @* com_wrptr = cur_wrptr;`
58			`endgenerate`
59
60			`assign c_drdy = !full & enable;`
61
62			`always @*`
63			`begin`
64			`if (cur_wrptr[asz-1:0] == bound_high)`
65			`begin`
66			`wrptr_p1[asz-1:0] = bound_low;`
67			`end`
68			`else`
69			`wrptr_p1 = cur_wrptr + 1;`
70
71			`empty = (cur_wrptr == rdptr) & !full;`
72			`nxt_full = (wrptr_p1 == rdptr);`
73
74			`if ((commit == 1) && c_abort)`
75			`begin`
76			`nxt_wrptr = com_wrptr;`
77			`end`
78			`else if (enable & c_srdy & !full)`
79			`begin`
80			`nxt_wrptr = wrptr_p1;`
81			`mem_we = 1;`
82			`end`
83			`else`
84			`begin`
85			`nxt_wrptr = cur_wrptr;`
86			`mem_we = 0;`
87			`end`
88			`end`
89
90			`always @(posedge clk)`
91			`begin`
92			`if (reset)`
93			`begin`
94			cur_wrptr <= `SDLIB_DELAY bound_low;
95			full <= `SDLIB_DELAY 0;
96			`end`
97			`else`
98			`begin`
99			cur_wrptr <= `SDLIB_DELAY nxt_wrptr;
100			full <= `SDLIB_DELAY nxt_full;
101			`end // else: !if(reset)`
102			`end // always @ (posedge clk)`
103
104			`generate if (commit)`
105			`always @*`
106			`begin`
107			`if (enable & c_commit & !c_abort & c_srdy & !full)`
108			`nxt_com_wrptr = wrptr_p1;`
109			`else`
110			`nxt_com_wrptr = com_wrptr;`
111			`end`
112
113			`always @(posedge clk)`
114			`begin`
115			`if (reset)`
116			com_wrptr <= `SDLIB_DELAY bound_low;
117			`else`
118			com_wrptr <= `SDLIB_DELAY nxt_com_wrptr;
119			`end`
120			`endgenerate`
121
122			`endmodule // fifo_head`
123

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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [buffers/] [sd_fifo_head_b.v] - Blame information for rev 2