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//----------------------------------------------------------------------
// Srdy/Drdy FIFO Tail "B"
//
// Building block for FIFOs.  The "B" (big) FIFO is design for larger FIFOs
// based around memories, with sizes that may not be a power of 2.
//
// The bound inputs allow multiple FIFO controllers to share a single
// memory.  The enable input is for arbitration between multiple FIFO
// controllers, or between the fifo head and tail controllers on a
// single port memory.
//
// The commit parameter enables read/commit behavior.  This creates
// two read pointers, one which is used for reading from memory and
// a commit pointer which is sent to the head block.  The abort behavior
// has a 3-cycle performance penalty due to pipeline flush.
//
// The FIFO tail assumes a memory with one-cycle read latency, and
// has output buffering to compensate for this.
//
// Naming convention: c = consumer, p = producer, i = internal interface
//----------------------------------------------------------------------
// Author: Guy Hutchison
//
// This block is uncopyrighted and released into the public domain.
//----------------------------------------------------------------------
 
// Clocking statement for synchronous blocks.  Default is for
// posedge clocking and positive async reset
`ifndef SDLIB_CLOCKING
 `define SDLIB_CLOCKING posedge clk or posedge reset
`endif
 
// delay unit for nonblocking assigns, default is to #1
`ifndef SDLIB_DELAY
 `define SDLIB_DELAY #1
`endif
 
 
module sd_fifo_tail_b
  #(parameter width=8,
    parameter depth=16,
    parameter commit=0,
    parameter asz=$clog2(depth),
    parameter usz=$clog2(depth+1)
    )
    (
     input       clk,
     input       reset,
     input       enable,
 
     input [asz-1:0]      bound_low,
     input [asz-1:0]      bound_high,
 
     output reg [asz-1:0]   cur_rdptr,
     output reg [asz-1:0]   com_rdptr,
     input  [asz-1:0]       wrptr,
     output reg           mem_re,
     input                mem_we,
 
     output reg [usz:0]   p_usage,
 
     output               p_srdy,
     input                p_drdy,
     input                p_commit,
     input                p_abort,
     input [width-1:0]    mem_rd_data,
     output [width-1:0]   p_data
     );
 
  reg [asz-1:0]           nxt_cur_rdptr;
  reg [asz-1:0]           cur_rdptr_p1;
  reg                   empty, full;
 
  reg                   nxt_irdy;
 
  reg [width-1:0]       hold_a, hold_b;
  reg                   valid_a, valid_b;
  reg                   prev_re;
  reg [usz:0]           tmp_usage;
  reg [usz:0]           fifo_size;
  wire                  rbuf1_drdy;
  wire                  ip_srdy, ip_drdy;
  wire [width-1:0]       ip_data;
 
  // Stage 1 -- Read pipeline
  // issue a read if:
  //   1) we are enabled
  //   2) valid_a is 0, OR
  //   3) valid_b is 0, OR
  //   4) valid_a && valid_b && trdy
  always @*
    begin
 
      if (cur_rdptr[asz-1:0] == (bound_high))
        begin
          cur_rdptr_p1[asz-1:0] = bound_low;
        end
      else
        cur_rdptr_p1 = cur_rdptr + 1;
 
      empty = (wrptr == cur_rdptr);
 
      if (commit && p_abort)
        begin
          nxt_cur_rdptr = com_rdptr;
          mem_re = 0;
        end
//      else if (enable & !empty & (!valid_a | (!prev_re & !valid_b) | 
//                             (valid_a & valid_b & p_drdy)))
      else if (enable & !empty & ip_drdy)
        begin
          nxt_cur_rdptr = cur_rdptr_p1;
          mem_re = 1;
        end
      else
        begin
          nxt_cur_rdptr = cur_rdptr;
          mem_re = 0;
        end // else: !if(enable & !empty & (!valid_a | !valid_b |...
 
      fifo_size = (bound_high - bound_low + 1);
      tmp_usage = wrptr[asz-1:0] - cur_rdptr[asz-1:0];
      if (~tmp_usage[usz])
        p_usage = tmp_usage[usz-1:0];
      else
        p_usage = fifo_size - (cur_rdptr[asz-1:0] - wrptr[asz-1:0]);
    end // always @ *
 
/* -----\/----- EXCLUDED -----\/-----
  // alternate usage calc
  reg [asz-1:0] prev_wr;
  reg [asz:0] usage2, nxt_usage2;
  wire        lcl_wr_en;
  //assign lcl_wr_en = (prev_wr0 != wrptr[0]);
 
  always @(posedge clk)
    begin
      if (reset)
        begin
          /-*AUTORESET*-/
          // Beginning of autoreset for uninitialized flops
          usage2 <= {(1+(asz)){1'b0}};
          // End of automatics
        end
      else
        begin
          usage2   <= #1 nxt_usage2;
        end
    end
 
  always @*
    begin
      if (mem_re & !mem_we)
        nxt_usage2 = usage2 - 1;
      else if (!mem_re & mem_we)
        nxt_usage2 = usage2 + 1;
      else
        nxt_usage2 = usage2;
    end
 -----/\----- EXCLUDED -----/\----- */
 
  always @(posedge clk)
    begin
      if (reset)
        cur_rdptr <= `SDLIB_DELAY bound_low;
      else
        cur_rdptr <= `SDLIB_DELAY nxt_cur_rdptr;
    end
 
  reg [asz-1:0]  rdaddr_s0, rdaddr_a, rdaddr_b;
  reg [asz-1:0]  nxt_com_rdptr;
  generate
    if (commit == 1)
      begin : gen_s0
 
        always @(posedge clk)
          begin
            if (reset)
              com_rdptr <= `SDLIB_DELAY bound_low;
            else
              com_rdptr <= `SDLIB_DELAY nxt_com_rdptr;
 
            if (mem_re)
              rdaddr_s0 <= `SDLIB_DELAY cur_rdptr;
          end
      end
    else
      begin : gen_ns0
        always @*
          com_rdptr = cur_rdptr;
      end
  endgenerate
 
  // Stage 2 -- read buffering
  always @(`SDLIB_CLOCKING)
    begin
      if (reset)
        begin
          prev_re <= `SDLIB_DELAY 0;
        end
      else
        begin
          if (commit && p_abort)
            prev_re <= `SDLIB_DELAY 0;
          else
            prev_re <= `SDLIB_DELAY mem_re;
        end // else: !if(reset)
    end // always @ (`SDLIB_CLOCKING)
 
  generate
    if (commit == 1)
      begin : gen_s2
        wire [asz-1:0] ip_rdaddr, p_rdaddr;
 
        sd_input #(asz+width) rbuf1
          (.clk (clk), .reset (p_abort | reset),
           .c_srdy (prev_re),
           .c_drdy (rbuf1_drdy),
           .c_data ({rdaddr_s0,mem_rd_data}),
           .ip_srdy (ip_srdy), .ip_drdy (ip_drdy),
           .ip_data ({ip_rdaddr,ip_data}));
 
        sd_output #(asz+width) rbuf2
          (.clk (clk), .reset (p_abort | reset),
           .ic_srdy (ip_srdy),
           .ic_drdy (ip_drdy),
           .ic_data ({ip_rdaddr,ip_data}),
           .p_srdy (p_srdy), .p_drdy (p_drdy),
           .p_data ({p_rdaddr,p_data}));
 
        always @*
          begin
            if (p_commit & p_srdy & p_drdy)
              nxt_com_rdptr = p_rdaddr;
            else
              nxt_com_rdptr = com_rdptr;
          end
      end // if (commit == 1)
    else
      begin : gen_ns2
        sd_input #(width) rbuf1
          (.clk (clk), .reset (p_abort | reset),
           .c_srdy (prev_re),
           .c_drdy (rbuf1_drdy),
           .c_data (mem_rd_data),
           .ip_srdy (ip_srdy), .ip_drdy (ip_drdy),
           .ip_data (ip_data));
 
        sd_output #(width) rbuf2
          (.clk (clk), .reset (p_abort | reset),
           .ic_srdy (ip_srdy),
           .ic_drdy (ip_drdy),
           .ic_data (ip_data),
           .p_srdy (p_srdy), .p_drdy (p_drdy),
           .p_data (p_data));
      end // else: !if(commit == 1)
  endgenerate
 
endmodule // it_fifo

Line No.	Rev	Author	Line
1	2	ghutchis	`//----------------------------------------------------------------------`
2			`// Srdy/Drdy FIFO Tail "B"`
3			`//`
4			`// Building block for FIFOs. The "B" (big) FIFO is design for larger FIFOs`
5			`// based around memories, with sizes that may not be a power of 2.`
6			`//`
7			`// The bound inputs allow multiple FIFO controllers to share a single`
8			`// memory. The enable input is for arbitration between multiple FIFO`
9			`// controllers, or between the fifo head and tail controllers on a`
10			`// single port memory.`
11			`//`
12			`// The commit parameter enables read/commit behavior. This creates`
13			`// two read pointers, one which is used for reading from memory and`
14			`// a commit pointer which is sent to the head block. The abort behavior`
15			`// has a 3-cycle performance penalty due to pipeline flush.`
16			`//`
17			`// The FIFO tail assumes a memory with one-cycle read latency, and`
18			`// has output buffering to compensate for this.`
19			`//`
20			`// Naming convention: c = consumer, p = producer, i = internal interface`
21			`//----------------------------------------------------------------------`
22			`// Author: Guy Hutchison`
23			`//`
24			`// This block is uncopyrighted and released into the public domain.`
25			`//----------------------------------------------------------------------`
26
27			`// Clocking statement for synchronous blocks. Default is for`
28			`// posedge clocking and positive async reset`
29			`ifndef SDLIB_CLOCKING
30			`define SDLIB_CLOCKING posedge clk or posedge reset
31			`endif
32
33			`// delay unit for nonblocking assigns, default is to #1`
34			`ifndef SDLIB_DELAY
35			`define SDLIB_DELAY #1
36			`endif
37
38
39			`module sd_fifo_tail_b`
40			`#(parameter width=8,`
41			`parameter depth=16,`
42			`parameter commit=0,`
43	16	ghutchis	`parameter asz=$clog2(depth),`
44			`parameter usz=$clog2(depth+1)`
45			`)`
46	2	ghutchis	`(`
47			`input clk,`
48			`input reset,`
49			`input enable,`
50
51			`input [asz-1:0] bound_low,`
52			`input [asz-1:0] bound_high,`
53
54			`output reg [asz-1:0] cur_rdptr,`
55			`output reg [asz-1:0] com_rdptr,`
56			`input [asz-1:0] wrptr,`
57			`output reg mem_re,`
58	13	ghutchis	`input mem_we,`
59	2	ghutchis
60	16	ghutchis	`output reg [usz:0] p_usage,`
61	2	ghutchis
62			`output p_srdy,`
63			`input p_drdy,`
64			`input p_commit,`
65			`input p_abort,`
66			`input [width-1:0] mem_rd_data,`
67			`output [width-1:0] p_data`
68			`);`
69
70			`reg [asz-1:0] nxt_cur_rdptr;`
71			`reg [asz-1:0] cur_rdptr_p1;`
72			`reg empty, full;`
73
74			`reg nxt_irdy;`
75
76			`reg [width-1:0] hold_a, hold_b;`
77			`reg valid_a, valid_b;`
78			`reg prev_re;`
79	16	ghutchis	`reg [usz:0] tmp_usage;`
80			`reg [usz:0] fifo_size;`
81	6	ghutchis	`wire rbuf1_drdy;`
82			`wire ip_srdy, ip_drdy;`
83			`wire [width-1:0] ip_data;`
84	2	ghutchis
85			`// Stage 1 -- Read pipeline`
86			`// issue a read if:`
87			`// 1) we are enabled`
88			`// 2) valid_a is 0, OR`
89			`// 3) valid_b is 0, OR`
90			`// 4) valid_a && valid_b && trdy`
91			`always @*`
92			`begin`
93
94			`if (cur_rdptr[asz-1:0] == (bound_high))`
95			`begin`
96			`cur_rdptr_p1[asz-1:0] = bound_low;`
97			`end`
98			`else`
99			`cur_rdptr_p1 = cur_rdptr + 1;`
100
101			`empty = (wrptr == cur_rdptr);`
102
103			`if (commit && p_abort)`
104			`begin`
105			`nxt_cur_rdptr = com_rdptr;`
106			`mem_re = 0;`
107			`end`
108	6	ghutchis	`// else if (enable & !empty & (!valid_a \| (!prev_re & !valid_b) \|`
109			`// (valid_a & valid_b & p_drdy)))`
110			`else if (enable & !empty & ip_drdy)`
111	2	ghutchis	`begin`
112			`nxt_cur_rdptr = cur_rdptr_p1;`
113			`mem_re = 1;`
114			`end`
115			`else`
116			`begin`
117			`nxt_cur_rdptr = cur_rdptr;`
118			`mem_re = 0;`
119			`end // else: !if(enable & !empty & (!valid_a \| !valid_b \|...`
120
121			`fifo_size = (bound_high - bound_low + 1);`
122			`tmp_usage = wrptr[asz-1:0] - cur_rdptr[asz-1:0];`
123	16	ghutchis	`if (~tmp_usage[usz])`
124			`p_usage = tmp_usage[usz-1:0];`
125	2	ghutchis	`else`
126	16	ghutchis	`p_usage = fifo_size - (cur_rdptr[asz-1:0] - wrptr[asz-1:0]);`
127	13	ghutchis	`end // always @ *`
128
129			`/* -----\/----- EXCLUDED -----\/-----`
130			`// alternate usage calc`
131			`reg [asz-1:0] prev_wr;`
132			`reg [asz:0] usage2, nxt_usage2;`
133			`wire lcl_wr_en;`
134			`//assign lcl_wr_en = (prev_wr0 != wrptr[0]);`
135
136			`always @(posedge clk)`
137			`begin`
138			`if (reset)`
139			`begin`
140			`/-AUTORESET-/`
141			`// Beginning of autoreset for uninitialized flops`
142			`usage2 <= {(1+(asz)){1'b0}};`
143			`// End of automatics`
144			`end`
145			`else`
146			`begin`
147			`usage2 <= #1 nxt_usage2;`
148			`end`
149	2	ghutchis	`end`
150	13	ghutchis
151			`always @*`
152			`begin`
153			`if (mem_re & !mem_we)`
154			`nxt_usage2 = usage2 - 1;`
155			`else if (!mem_re & mem_we)`
156			`nxt_usage2 = usage2 + 1;`
157			`else`
158			`nxt_usage2 = usage2;`
159			`end`
160			`-----/\----- EXCLUDED -----/\----- */`
161	2	ghutchis
162			`always @(posedge clk)`
163			`begin`
164			`if (reset)`
165			cur_rdptr <= `SDLIB_DELAY bound_low;
166			`else`
167			cur_rdptr <= `SDLIB_DELAY nxt_cur_rdptr;
168			`end`
169
170	11	ghutchis	`reg [asz-1:0] rdaddr_s0, rdaddr_a, rdaddr_b;`
171			`reg [asz-1:0] nxt_com_rdptr;`
172	2	ghutchis	`generate`
173			`if (commit == 1)`
174			`begin : gen_s0`
175
176			`always @(posedge clk)`
177			`begin`
178			`if (reset)`
179			com_rdptr <= `SDLIB_DELAY bound_low;
180			`else`
181			com_rdptr <= `SDLIB_DELAY nxt_com_rdptr;
182
183			`if (mem_re)`
184			rdaddr_s0 <= `SDLIB_DELAY cur_rdptr;
185			`end`
186			`end`
187			`else`
188			`begin : gen_ns0`
189			`always @*`
190			`com_rdptr = cur_rdptr;`
191			`end`
192			`endgenerate`
193
194			`// Stage 2 -- read buffering`
195			always @(`SDLIB_CLOCKING)
196			`begin`
197			`if (reset)`
198			`begin`
199			prev_re <= `SDLIB_DELAY 0;
200	6	ghutchis	`end`
201	2	ghutchis	`else`
202			`begin`
203			`if (commit && p_abort)`
204			prev_re <= `SDLIB_DELAY 0;
205			`else`
206			prev_re <= `SDLIB_DELAY mem_re;
207	6	ghutchis	`end // else: !if(reset)`
208			end // always @ (`SDLIB_CLOCKING)
209	2	ghutchis
210			`generate`
211			`if (commit == 1)`
212	11	ghutchis	`begin : gen_s2`
213	6	ghutchis	`wire [asz-1:0] ip_rdaddr, p_rdaddr;`
214	2	ghutchis
215	6	ghutchis	`sd_input #(asz+width) rbuf1`
216			`(.clk (clk), .reset (p_abort \| reset),`
217			`.c_srdy (prev_re),`
218			`.c_drdy (rbuf1_drdy),`
219			`.c_data ({rdaddr_s0,mem_rd_data}),`
220			`.ip_srdy (ip_srdy), .ip_drdy (ip_drdy),`
221			`.ip_data ({ip_rdaddr,ip_data}));`
222
223			`sd_output #(asz+width) rbuf2`
224			`(.clk (clk), .reset (p_abort \| reset),`
225			`.ic_srdy (ip_srdy),`
226			`.ic_drdy (ip_drdy),`
227			`.ic_data ({ip_rdaddr,ip_data}),`
228			`.p_srdy (p_srdy), .p_drdy (p_drdy),`
229			`.p_data ({p_rdaddr,p_data}));`
230	2	ghutchis
231			`always @*`
232			`begin`
233	14	ghutchis	`if (p_commit & p_srdy & p_drdy)`
234	6	ghutchis	`nxt_com_rdptr = p_rdaddr;`
235	2	ghutchis	`else`
236			`nxt_com_rdptr = com_rdptr;`
237			`end`
238	6	ghutchis	`end // if (commit == 1)`
239			`else`
240	11	ghutchis	`begin : gen_ns2`
241	6	ghutchis	`sd_input #(width) rbuf1`
242			`(.clk (clk), .reset (p_abort \| reset),`
243			`.c_srdy (prev_re),`
244			`.c_drdy (rbuf1_drdy),`
245			`.c_data (mem_rd_data),`
246			`.ip_srdy (ip_srdy), .ip_drdy (ip_drdy),`
247			`.ip_data (ip_data));`
248
249			`sd_output #(width) rbuf2`
250			`(.clk (clk), .reset (p_abort \| reset),`
251			`.ic_srdy (ip_srdy),`
252			`.ic_drdy (ip_drdy),`
253			`.ic_data (ip_data),`
254			`.p_srdy (p_srdy), .p_drdy (p_drdy),`
255			`.p_data (p_data));`
256			`end // else: !if(commit == 1)`
257	2	ghutchis	`endgenerate`
258
259			`endmodule // it_fifo`

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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [buffers/] [sd_fifo_tail_b.v] - Blame information for rev 16