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//----------------------------------------------------------------------
//  Srdy/drdy mirrored fork
//
//  Used when a single item of data needs to be used by more than one
//  block, and all blocks may finish at different times.  This creates
//  separate srdy/drdy signals for each block, and holds drdy to the
//  sender until all blocks have individually asserted drdy.
//
//  The input c_dst_vld allows the data to be selectively sent to some
//  or all of the downstream endpoints.  At least one bit in c_dst_vld
//  must be asserted with c_srdy.  If this functionality is not desired
//  the input should be tied to 0.
//
// Naming convention: c = consumer, p = producer, i = internal interface
//----------------------------------------------------------------------
//  Author: Guy Hutchison
//
// This block is uncopyrighted and released into the public domain.
//----------------------------------------------------------------------
 
// Clocking statement for synchronous blocks.  Default is for
// posedge clocking and positive async reset
`ifndef SDLIB_CLOCKING
 `define SDLIB_CLOCKING posedge clk or posedge reset
`endif
 
// delay unit for nonblocking assigns, default is to #1
`ifndef SDLIB_DELAY
 `define SDLIB_DELAY #1
`endif
 
module sd_mirror
  #(parameter mirror=2,
    parameter width=128)
  (input        clk,
   input        reset,
 
   input              c_srdy,
   output reg         c_drdy,
   input [width-1:0]  c_data,
   input [mirror-1:0] c_dst_vld,
 
   output reg [mirror-1:0] p_srdy,
   input [mirror-1:0]      p_drdy,
   output reg [width-1:0]  p_data
   );
 
  reg                    state, nxt_state;
  reg [mirror-1:0]        nxt_p_srdy;
  reg                    load;
 
  always @(posedge clk)
    if (load)
      p_data <= `SDLIB_DELAY c_data;
 
  always @*
    begin
      nxt_p_srdy = p_srdy;
      nxt_state    = state;
      c_drdy       = 0;
      load         = 0;
 
      case (state)
 
          begin
            c_drdy = 1'b1;
            if (c_srdy)
              begin
                if (c_dst_vld == {mirror{1'b0}})
                  nxt_p_srdy = {mirror{1'b1}};
                else
                  nxt_p_srdy = c_dst_vld;
                nxt_state    = 1;
                load         = 1;
              end
          end
 
        1 :
          begin
            nxt_p_srdy = p_srdy & ~p_drdy;
 
            if (p_srdy == {mirror{1'b0}})
              begin
                nxt_state = 1'b0;
              end
          end
      endcase
    end
 
  always @(`SDLIB_CLOCKING)
    begin
      if (reset)
        begin
          p_srdy   <= `SDLIB_DELAY {mirror{1'b0}};
          state    <= `SDLIB_DELAY 1'b0;
        end
      else
        begin
          p_srdy   <= `SDLIB_DELAY nxt_p_srdy;
          state    <= `SDLIB_DELAY nxt_state;
        end
    end
 
endmodule // sd_mirror

Line No.	Rev	Author	Line
1	2	ghutchis	`//----------------------------------------------------------------------`
2			`// Srdy/drdy mirrored fork`
3			`//`
4			`// Used when a single item of data needs to be used by more than one`
5			`// block, and all blocks may finish at different times. This creates`
6			`// separate srdy/drdy signals for each block, and holds drdy to the`
7			`// sender until all blocks have individually asserted drdy.`
8			`//`
9			`// The input c_dst_vld allows the data to be selectively sent to some`
10			`// or all of the downstream endpoints. At least one bit in c_dst_vld`
11			`// must be asserted with c_srdy. If this functionality is not desired`
12			`// the input should be tied to 0.`
13			`//`
14			`// Naming convention: c = consumer, p = producer, i = internal interface`
15			`//----------------------------------------------------------------------`
16			`// Author: Guy Hutchison`
17			`//`
18			`// This block is uncopyrighted and released into the public domain.`
19			`//----------------------------------------------------------------------`
20
21			`// Clocking statement for synchronous blocks. Default is for`
22			`// posedge clocking and positive async reset`
23			`ifndef SDLIB_CLOCKING
24			`define SDLIB_CLOCKING posedge clk or posedge reset
25			`endif
26
27			`// delay unit for nonblocking assigns, default is to #1`
28			`ifndef SDLIB_DELAY
29			`define SDLIB_DELAY #1
30			`endif
31
32			`module sd_mirror`
33			`#(parameter mirror=2,`
34			`parameter width=128)`
35			`(input clk,`
36			`input reset,`
37
38			`input c_srdy,`
39			`output reg c_drdy,`
40			`input [width-1:0] c_data,`
41			`input [mirror-1:0] c_dst_vld,`
42
43			`output reg [mirror-1:0] p_srdy,`
44			`input [mirror-1:0] p_drdy,`
45			`output reg [width-1:0] p_data`
46			`);`
47
48			`reg state, nxt_state;`
49			`reg [mirror-1:0] nxt_p_srdy;`
50			`reg load;`
51
52			`always @(posedge clk)`
53			`if (load)`
54			p_data <= `SDLIB_DELAY c_data;
55
56			`always @*`
57			`begin`
58			`nxt_p_srdy = p_srdy;`
59			`nxt_state = state;`
60			`c_drdy = 0;`
61			`load = 0;`
62
63			`case (state)`
64
65			`begin`
66			`c_drdy = 1'b1;`
67			`if (c_srdy)`
68			`begin`
69			`if (c_dst_vld == {mirror{1'b0}})`
70			`nxt_p_srdy = {mirror{1'b1}};`
71			`else`
72			`nxt_p_srdy = c_dst_vld;`
73			`nxt_state = 1;`
74			`load = 1;`
75			`end`
76			`end`
77
78			`1 :`
79			`begin`
80			`nxt_p_srdy = p_srdy & ~p_drdy;`
81
82			`if (p_srdy == {mirror{1'b0}})`
83			`begin`
84			`nxt_state = 1'b0;`
85			`end`
86			`end`
87			`endcase`
88			`end`
89
90			always @(`SDLIB_CLOCKING)
91			`begin`
92			`if (reset)`
93			`begin`
94			p_srdy <= `SDLIB_DELAY {mirror{1'b0}};
95			state <= `SDLIB_DELAY 1'b0;
96			`end`
97			`else`
98			`begin`
99			p_srdy <= `SDLIB_DELAY nxt_p_srdy;
100			state <= `SDLIB_DELAY nxt_state;
101			`end`
102			`end`
103
104			`endmodule // sd_mirror`

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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [forks/] [sd_mirror.v] - Blame information for rev 2