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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [memory/] [behave2p_mem.v] - Blame information for rev 6

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Line No. Rev Author Line
1 2 ghutchis
//----------------------------------------------------------------------
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// Author: Guy Hutchison
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//
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// This block is uncopyrighted and released into the public domain.
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//----------------------------------------------------------------------
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module behave2p_mem
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  #(parameter width=8,
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    parameter depth=256,
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    parameter addr_sz=$clog2(depth))
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  (/*AUTOARG*/
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  // Outputs
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  d_out,
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  // Inputs
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  wr_en, rd_en, wr_clk, rd_clk, d_in, rd_addr, wr_addr
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  );
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  input        wr_en, rd_en, wr_clk;
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  input        rd_clk;
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  input [width-1:0] d_in;
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  input [addr_sz-1:0] rd_addr, wr_addr;
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  output [width-1:0]  d_out;
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  reg [addr_sz-1:0] r_addr;
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  reg [width-1:0]   array[0:depth-1];
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  always @(posedge wr_clk)
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    begin
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      if (wr_en)
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        begin
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          array[wr_addr] <= #1 d_in;
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        end
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    end
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  always @(posedge rd_clk)
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    begin
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      if (rd_en)
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        begin
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          r_addr <= #1 rd_addr;
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        end
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    end // always @ (posedge clk)
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  assign d_out = array[r_addr];
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endmodule

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