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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [utility/] [llmanager_refcount.v] - Blame information for rev 30

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1 30 ghutchis 
module llmanager_refcount
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  #(parameter     lpsz = 8,
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    parameter     refsz = 3)
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  (
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   input clk,
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   input reset,
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   input            drq_srdy,
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   output reg       drq_drdy,
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   input [lpsz-1:0]         drq_start_page,
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   input [lpsz-1:0]         drq_end_page,
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   output reg reclaim_srdy,
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   input      reclaim_drdy,
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   output reg [lpsz-1:0] reclaim_start_page,
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   output reg [lpsz-1:0] reclaim_end_page,
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   // reference count update interface
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   input                  refup_srdy,
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   output reg             refup_drdy,
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   input [lpsz-1:0]       refup_page,
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   input [refsz-1:0]      refup_count,
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   // reference count memory interface
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   output reg                ref_wr_en,
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   output reg [lpsz-1:0]     ref_wr_addr,
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   output reg [refsz-1:0]    ref_wr_data,
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   output reg [lpsz-1:0]     ref_rd_addr,
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   output reg                ref_rd_en,
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   input [refsz-1:0]         ref_rd_data
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   );
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  reg [lpsz-1:0]          dref_start_addr, nxt_dref_start_addr;
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  reg [lpsz-1:0]          dref_end_addr, nxt_dref_end_addr;
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  reg [2:0]               state, nxt_state;
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  localparam s_idle = 0, s_dreq = 1, s_reclaim = 2;
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  always @*
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    begin
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      reclaim_srdy = 0;
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      reclaim_start_page = 0;
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      reclaim_end_page = 0;
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      ref_wr_en = 0;
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      ref_wr_addr = 0;
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      ref_wr_data = 0;
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      ref_rd_addr = 0;
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      ref_rd_en = 0;
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      drq_drdy = 0;
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      refup_drdy = 0;
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      nxt_state = state;
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      nxt_dref_start_addr = dref_start_addr;
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      nxt_dref_end_addr   = dref_end_addr;
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      case (1'b1)
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        state[s_idle] :
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          begin
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            refup_drdy = 1;
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            if (refup_srdy)
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              begin
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                ref_wr_en = 1;
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                ref_wr_addr = refup_page;
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                ref_wr_data = refup_count;
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              end
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            else if (drq_srdy)
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              begin
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                ref_rd_en = 1;
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                ref_rd_addr = drq_start_page;
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                nxt_state = 1 << s_dreq;
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                nxt_dref_start_addr = drq_start_page;
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                nxt_dref_end_addr   = drq_end_page;
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              end
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          end // case: s_idle
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        state[s_dreq] :
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          begin
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            drq_drdy = 1;
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            ref_wr_en = 1;
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            ref_wr_addr = dref_start_addr;
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            ref_wr_data = ref_rd_data - 1;
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            if (ref_rd_data == 1)
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              nxt_state = 1 << s_reclaim;
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            else
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              nxt_state = 1 << s_idle;
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          end
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        state[s_reclaim] :
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          begin
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            reclaim_srdy = 1;
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            reclaim_start_page = dref_start_addr;
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            reclaim_end_page = dref_end_addr;
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            if (reclaim_drdy)
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              nxt_state = 1 << s_idle;
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          end
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      endcase // case (1'b1)
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    end // always @ *
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  always @(posedge clk)
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    begin
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      if (reset)
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        begin
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          state <= 1 << s_idle;
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        end
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      else
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        begin
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          state <= nxt_state;
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        end
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    end
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  always @(posedge clk)
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    begin
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      dref_start_addr <= nxt_dref_start_addr;
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      dref_end_addr   <= nxt_dref_end_addr;
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    end
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endmodule // llmanager_refcount

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