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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [utility/] [sd_sync.v] - Blame information for rev 25

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//----------------------------------------------------------------------
// Srdy/Drdy Sync Block
//
// Provides synchronization across clock domains for an srdy/drdy
// pair.  Assumes low utilization; for high utilization see sd_fifo_a.
//
// Only syncs control signals, data can be passed directly to the
// receiver.
//
// Naming convention: c = consumer, p = producer
//----------------------------------------------------------------------
//  Author: Guy Hutchison
//
// This block is uncopyrighted and released into the public domain.
//----------------------------------------------------------------------
 
// delay unit for nonblocking assigns, default is to #1
`ifndef SDLIB_DELAY
 `define SDLIB_DELAY #1
`endif
 
module sd_sync
  #(parameter edge_det = 0)
  (
   input       c_clk,
   input       c_reset,
   input       c_srdy,
   output reg  c_drdy,
 
   input       p_clk,
   input       p_reset,
   output reg  p_srdy,
   input       p_drdy
   );
 
  reg          launch_a, nxt_launch_a;
 
  reg          sync_ack_b, ack_b;
  reg [1:0]    psync_b; // pulse sync A to B
  reg          p_ack;
  reg          p_state, nxt_p_state;
  reg [1:0]    c_state, nxt_c_state;
 
  localparam ps_idle = 0, ps_ack = 1;
  localparam cs_idle = 0, cs_req = 1, cs_clear = 2;
 
  //------------------------------------------------------------
  // Consumer Clock Domain
  //------------------------------------------------------------
 
  always @*
    begin
      nxt_launch_a = 0;
      c_drdy = 0;
      nxt_c_state = c_state;
 
      case (c_state)
        cs_idle :
          begin
            if (c_srdy)
              begin
                nxt_launch_a = 1;
                nxt_c_state  = cs_req;
              end
          end
 
        cs_req :
          begin
            nxt_launch_a = 1;
 
            if (ack_b)
              begin
                c_drdy = 1;
                nxt_c_state = cs_clear;
              end
          end
 
        cs_clear :
          begin
            if (!ack_b)
              nxt_c_state = cs_idle;
          end
 
        default : nxt_c_state = cs_idle;
      endcase
    end // always @ *
 
 
  always @(posedge c_clk or posedge c_reset)
    begin
      if (c_reset)
        begin
          launch_a <= `SDLIB_DELAY 1'b0;
          c_state  <= `SDLIB_DELAY cs_idle;
        end
      else
        begin
          launch_a <= `SDLIB_DELAY nxt_launch_a;
          c_state  <= `SDLIB_DELAY nxt_c_state;
        end
    end
 
  always @(posedge c_clk)
    begin
      ack_b      <= `SDLIB_DELAY sync_ack_b;
      sync_ack_b <= `SDLIB_DELAY p_ack;
    end
 
  //------------------------------------------------------------
  // Producer Clock Domain
  //------------------------------------------------------------
 
  always @(posedge p_clk or posedge p_reset)
    begin
      if (p_reset)
        p_state <= `SDLIB_DELAY ps_idle;
      else
        p_state <= `SDLIB_DELAY nxt_p_state;
    end
 
  always @(posedge p_clk)
    begin
      psync_b   <= `SDLIB_DELAY { launch_a, psync_b[1] };
    end
 
  always @*
    begin
      p_ack = 0;
      p_srdy = 0;
      nxt_p_state = p_state;
 
      case (p_state)
        ps_idle :
          begin
            p_srdy = psync_b[0];
 
            if (psync_b[0] & p_drdy)
              begin
                nxt_p_state = ps_ack;
              end
          end
 
        ps_ack :
          begin
            p_srdy = 0;
            p_ack  = 1;
 
            if (!psync_b[0])
              nxt_p_state = ps_idle;
          end
 
      endcase // case (p_state)
    end // always @ *
 
endmodule // sd_sync

Line No.	Rev	Author	Line
1	25	ghutchis	`//----------------------------------------------------------------------`
2			`// Srdy/Drdy Sync Block`
3			`//`
4			`// Provides synchronization across clock domains for an srdy/drdy`
5			`// pair. Assumes low utilization; for high utilization see sd_fifo_a.`
6			`//`
7			`// Only syncs control signals, data can be passed directly to the`
8			`// receiver.`
9			`//`
10			`// Naming convention: c = consumer, p = producer`
11			`//----------------------------------------------------------------------`
12			`// Author: Guy Hutchison`
13			`//`
14			`// This block is uncopyrighted and released into the public domain.`
15			`//----------------------------------------------------------------------`
16
17			`// delay unit for nonblocking assigns, default is to #1`
18			`ifndef SDLIB_DELAY
19			`define SDLIB_DELAY #1
20			`endif
21
22			`module sd_sync`
23			`#(parameter edge_det = 0)`
24			`(`
25			`input c_clk,`
26			`input c_reset,`
27			`input c_srdy,`
28			`output reg c_drdy,`
29
30			`input p_clk,`
31			`input p_reset,`
32			`output reg p_srdy,`
33			`input p_drdy`
34			`);`
35
36			`reg launch_a, nxt_launch_a;`
37
38			`reg sync_ack_b, ack_b;`
39			`reg [1:0] psync_b; // pulse sync A to B`
40			`reg p_ack;`
41			`reg p_state, nxt_p_state;`
42			`reg [1:0] c_state, nxt_c_state;`
43
44			`localparam ps_idle = 0, ps_ack = 1;`
45			`localparam cs_idle = 0, cs_req = 1, cs_clear = 2;`
46
47			`//------------------------------------------------------------`
48			`// Consumer Clock Domain`
49			`//------------------------------------------------------------`
50
51			`always @*`
52			`begin`
53			`nxt_launch_a = 0;`
54			`c_drdy = 0;`
55			`nxt_c_state = c_state;`
56
57			`case (c_state)`
58			`cs_idle :`
59			`begin`
60			`if (c_srdy)`
61			`begin`
62			`nxt_launch_a = 1;`
63			`nxt_c_state = cs_req;`
64			`end`
65			`end`
66
67			`cs_req :`
68			`begin`
69			`nxt_launch_a = 1;`
70
71			`if (ack_b)`
72			`begin`
73			`c_drdy = 1;`
74			`nxt_c_state = cs_clear;`
75			`end`
76			`end`
77
78			`cs_clear :`
79			`begin`
80			`if (!ack_b)`
81			`nxt_c_state = cs_idle;`
82			`end`
83
84			`default : nxt_c_state = cs_idle;`
85			`endcase`
86			`end // always @ *`
87
88
89			`always @(posedge c_clk or posedge c_reset)`
90			`begin`
91			`if (c_reset)`
92			`begin`
93			launch_a <= `SDLIB_DELAY 1'b0;
94			c_state <= `SDLIB_DELAY cs_idle;
95			`end`
96			`else`
97			`begin`
98			launch_a <= `SDLIB_DELAY nxt_launch_a;
99			c_state <= `SDLIB_DELAY nxt_c_state;
100			`end`
101			`end`
102
103			`always @(posedge c_clk)`
104			`begin`
105			ack_b <= `SDLIB_DELAY sync_ack_b;
106			sync_ack_b <= `SDLIB_DELAY p_ack;
107			`end`
108
109			`//------------------------------------------------------------`
110			`// Producer Clock Domain`
111			`//------------------------------------------------------------`
112
113			`always @(posedge p_clk or posedge p_reset)`
114			`begin`
115			`if (p_reset)`
116			p_state <= `SDLIB_DELAY ps_idle;
117			`else`
118			p_state <= `SDLIB_DELAY nxt_p_state;
119			`end`
120
121			`always @(posedge p_clk)`
122			`begin`
123			psync_b <= `SDLIB_DELAY { launch_a, psync_b[1] };
124			`end`
125
126			`always @*`
127			`begin`
128			`p_ack = 0;`
129			`p_srdy = 0;`
130			`nxt_p_state = p_state;`
131
132			`case (p_state)`
133			`ps_idle :`
134			`begin`
135			`p_srdy = psync_b[0];`
136
137			`if (psync_b[0] & p_drdy)`
138			`begin`
139			`nxt_p_state = ps_ack;`
140			`end`
141			`end`
142
143			`ps_ack :`
144			`begin`
145			`p_srdy = 0;`
146			`p_ack = 1;`
147
148			`if (!psync_b[0])`
149			`nxt_p_state = ps_idle;`
150			`end`
151
152			`endcase // case (p_state)`
153			`end // always @ *`
154
155			`endmodule // sd_sync`

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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [utility/] [sd_sync.v] - Blame information for rev 25