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amulcock |
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---- ----
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---- ----
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---- This file is part of the srl_fifo project ----
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---- http://www.opencores.org/cores/srl_fifo ----
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---- ----
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---- Description ----
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---- Implementation of srl_fifo IP core according to ----
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---- srl_fifo IP core specification document. ----
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---- ----
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---- To Do: ----
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---- NA ----
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---- ----
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---- Author(s): ----
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---- Andrew Mulcock, amulcock@opencores.org ----
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---- ----
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----------------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2008 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------------
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-- ----
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-- CVS Revision History ----
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-- ----
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-- $Log: not supported by cvs2svn $ ----
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-- ----
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--
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-- quick description
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--
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-- Based upon the using a shift register as a fifo which has been
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-- around for years ( decades ), but really came of use to VHDL
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-- when the Xilinx FPGA's started having SRL's.
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--
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-- In my view, the definitive article on shift register logic fifo's
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-- comes from Mr Chapman at Xilinx, in the form of his BBFIFO
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-- tecXeclusive article, which as at early 2008, Xilinx have
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-- removed.
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--
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-- This version is for 'later' devices that have an inherent shift
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-- register of 32 bits.
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.NUMERIC_STD.all;
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entity srl_fifo_32 is
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generic ( width : integer := 8 ); -- set to how wide fifo is to be
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port(
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data_in : in std_logic_vector (width -1 downto 0);
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data_out : out std_logic_vector (width -1 downto 0);
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reset : in std_logic;
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write : in std_logic;
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read : in std_logic;
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full : out std_logic;
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half_full : out std_logic;
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data_present : out std_logic;
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clk : in std_logic
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);
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-- Declarations
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end srl_fifo_32 ;
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--
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------------------------------------------------------------------------------------
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--
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architecture rtl of srl_fifo_32 is
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--
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------------------------------------------------------------------------------------
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--
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------------------------------------------------------------------------------------
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--
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------------------------------------------------------------------------------------
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--
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constant srl_length : integer := 32; -- set to srl 'type' 16 or 32 bit length
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constant pointer_vec : integer := 5; -- set to number of bits needed to store pointer = log2(srl_length)
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type srl_array is array ( srl_length - 1 downto 0 ) of STD_LOGIC_VECTOR ( WIDTH - 1 downto 0 );
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signal fifo_store : srl_array;
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signal pointer : integer range 0 to srl_length - 1;
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signal pointer_zero : std_logic;
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signal pointer_full : std_logic;
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signal valid_write : std_logic;
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signal half_full_int : std_logic_vector( pointer_vec - 1 downto 0);
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signal empty : std_logic := '1';
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signal valid_count : std_logic ;
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------------------------------------------------------------------------------------
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--
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------------------------------------------------------------------------------------
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--
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begin
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-- Valid write, high when valid to write data to the store.
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valid_write <= '1' when ( read = '1' and write = '1' )
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or ( write = '1' and pointer_full = '0' ) else '0';
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-- data store SRL's
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data_srl :process( clk )
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begin
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if rising_edge( clk ) then
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if valid_write = '1' then
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fifo_store <= fifo_store( fifo_store'left - 1 downto 0) & data_in;
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end if;
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end if;
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end process;
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data_out <= fifo_store( pointer );
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process( clk)
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begin
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if rising_edge( clk ) then
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if reset = '1' then
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empty <= '1';
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elsif empty = '1' and write = '1' then
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empty <= '0';
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elsif pointer_zero = '1' and read = '1' and write = '0' then
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empty <= '1';
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end if;
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end if;
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end process;
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-- W R Action
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-- 0 0 pointer <= pointer
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-- 0 1 pointer <= pointer - 1 Read, but no write, so less data in counter
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-- 1 0 pointer <= pointer + 1 Write, but no read, so more data in fifo
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-- 1 1 pointer <= pointer Read and write, so same number of words in fifo
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--
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valid_count <= '1' when (
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(write = '1' and read = '0' and pointer_full = '0' and empty = '0' )
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or
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(write = '0' and read = '1' and pointer_zero = '0' )
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) else '0';
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process( clk )
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begin
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if rising_edge( clk ) then
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if valid_count = '1' then
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if write = '1' then
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pointer <= pointer + 1;
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else
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pointer <= pointer - 1;
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end if;
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end if;
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end if;
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end process;
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-- Detect when pointer is zero and maximum
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pointer_zero <= '1' when pointer = 0 else '0';
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pointer_full <= '1' when pointer = srl_length - 1 else '0';
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-- assign internal signals to outputs
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full <= pointer_full;
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half_full_int <= std_logic_vector(to_unsigned(pointer, pointer_vec));
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half_full <= half_full_int(half_full_int'left);
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data_present <= not( empty );
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end rtl;
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------------------------------------------------------------------------------------
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--
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------------------------------------------------------------------------------------
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