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[/] [srl_fifo/] [trunk/] [rtl/] [tb_srl_fifo_64.vhd] - Blame information for rev 7

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----------------------------------------------------------------------------
----                                                                                                                ----
----                                                                                                                ----
---- This file is part of the srl_fifo project                                              ----
---- http://www.opencores.org/cores/srl_fifo                                            ----
----                                                                                                                ----
---- Description                                                                                                ----
---- Implementation of srl_fifo IP core according to                    ----
---- srl_fifo IP core specification document.                                   ----
----                                                                                                                ----
---- To Do:                                                                                                         ----
----    NA                                                                                                          ----
----                                                                                                                ----
---- Author(s):                                                                                             ----
----   Andrew Mulcock, amulcock@opencores.org                                   ----
----                                                                                                                ----
----------------------------------------------------------------------------
----                                                                                                                ----
---- Copyright (C) 2008 Authors and OPENCORES.ORG                                       ----
----                                                                                                                ----
---- This source file may be used and distributed without                               ----
---- restriction provided that this copyright statement is not                  ----
---- removed from the file and that any derivative work contains                ----
---- the original copyright notice and the associated disclaimer.               ----
----                                                                                                                ----
---- This source file is free software; you can redistribute it                 ----
---- and/or modify it under the terms of the GNU Lesser General             ----
---- Public License as published by the Free Software Foundation;               ----
---- either version 2.1 of the License, or (at your option) any                 ----
---- later version.                                                                                             ----
----                                                                                                                ----
---- This source is distributed in the hope that it will be                             ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied         ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ----
---- PURPOSE. See the GNU Lesser General Public License for more                ----
---- details.                                                                                                   ----
----                                                                                                                ----
---- You should have received a copy of the GNU Lesser General              ----
---- Public License along with this source; if not, download it                 ----
---- from http://www.opencores.org/lgpl.shtml                                           ----
----                                                                                                                ----
----------------------------------------------------------------------------
--                                                                                                                      ----
-- CVS Revision History                                                                                 ----
--                                                                                                                      ----
-- $Log: not supported by cvs2svn $                                                                                                         ----
--                                                                                                                      ----
--
-- quick description
--
--  Based upon the using a shift register as a fifo which has been 
--   around for years ( decades ), but really came of use to VHDL 
--   when the Xilinx FPGA's started having SRL's. 
--
--  In my view, the definitive article on shift register logic fifo's 
--   comes from Mr Chapman at Xilinx, in the form of his BBFIFO
--    tecXeclusive article, which as at early 2008, Xilinx have
--     removed.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY tb_srl_fifo_64_vhd IS
END tb_srl_fifo_64_vhd;
 
ARCHITECTURE behavior OF tb_srl_fifo_64_vhd IS
 
constant width_tb : integer := 8;
 
        -- Component Declaration for the Unit Under Test (UUT)
        COMPONENT srl_fifo_64
    GENERIC ( width : integer := width_tb ); -- set to how wide fifo is to be
        PORT(
                data_in : IN std_logic_vector(width_tb - 1 downto 0);
                reset : IN std_logic;
                write : IN std_logic;
                read : IN std_logic;
                clk : IN std_logic;
                data_out : OUT std_logic_vector(width_tb -1  downto 0);
                full : OUT std_logic;
                half_full : OUT std_logic;
                data_present : OUT std_logic
                );
        END COMPONENT;
 
        --Inputs
        SIGNAL reset :  std_logic := '0';
        SIGNAL write :  std_logic := '0';
        SIGNAL read :  std_logic := '0';
        SIGNAL clk :  std_logic := '0';
        SIGNAL data_in :  std_logic_vector(width_tb - 1 downto 0) := (others=>'0');
 
        --Outputs
        SIGNAL data_out :  std_logic_vector(width_tb -1  downto 0);
        SIGNAL full :  std_logic;
        SIGNAL half_full :  std_logic;
        SIGNAL data_present :  std_logic;
 
BEGIN
 
        -- Instantiate the Unit Under Test (UUT)
        uut: srl_fifo_64
        GENERIC MAP (
        width => width_tb
        )
    PORT MAP(
                data_in => data_in,
                data_out => data_out,
                reset => reset,
                write => write,
                read => read,
                full => full,
                half_full => half_full,
                data_present => data_present,
                clk => clk
        );
 
        tb : PROCESS
        BEGIN
 
 
 
                -- Wait 100 ns for global reset to finish
                wait for 100 ns;
 
        wait until clk = '0';
        reset <= '0';
 
                -- Place stimulus here
 
    wait until clk = '0';  -- 0
    data_in <= X"AA";
    write <= '1';
 
    wait until clk = '0';   -- 1
    data_in <= X"55";
 
    wait until clk = '0';   -- 2
    data_in <= X"02";
    wait until clk = '0';   -- 3
    data_in <= X"03";
    wait until clk = '0';   -- 4
    data_in <= X"04";
    wait until clk = '0';   -- 5
    data_in <= X"05";
    wait until clk = '0';   -- 6
    data_in <= X"06";
    wait until clk = '0';   -- 7
    data_in <= X"07";
    wait until clk = '0';   -- 8
    data_in <= X"08";
    wait until clk = '0';   -- 9
    data_in <= X"09";
    wait until clk = '0';   -- A
    data_in <= X"A0";
    wait until clk = '0';   -- B
    data_in <= X"B0";
    wait until clk = '0';   -- C
    data_in <= X"C0";
    wait until clk = '0';   -- D
    data_in <= X"D0";
    wait until clk = '0';   -- E
    data_in <= X"E0";
    wait until clk = '0';   -- F
    data_in <= X"F0";
    wait until clk = '0';   -- 10
    data_in <= X"10";
    wait until clk = '0';   -- 11
    data_in <= X"11";
    wait until clk = '0';   -- 12
    data_in <= X"12";
    wait until clk = '0';   -- 13
    data_in <= X"13";
    wait until clk = '0';   -- 14
    data_in <= X"14";
    wait until clk = '0';   -- 15
    data_in <= X"15";
    wait until clk = '0';   -- 16
    data_in <= X"16";
    wait until clk = '0';   -- 17
    data_in <= X"17";
    wait until clk = '0';   -- 18
    data_in <= X"18";
    wait until clk = '0';   -- 19
    data_in <= X"19";
    wait until clk = '0';   -- 1A
    data_in <= X"1A";
    wait until clk = '0';   -- 1B
    data_in <= X"1B";
    wait until clk = '0';   -- 1C
    data_in <= X"1C";
    wait until clk = '0';   -- 1D
    data_in <= X"1D";
    wait until clk = '0';   -- 1E
    data_in <= X"1E";
    wait until clk = '0';   -- 1F
    data_in <= X"1F";
 
    --
 
    wait until clk = '0';  -- 20
    data_in <= X"20";
    write <= '1';
 
    wait until clk = '0';   -- 21
    data_in <= X"21";
 
    wait until clk = '0';   -- 22
    data_in <= X"22";
    wait until clk = '0';   -- 23
    data_in <= X"23";
    wait until clk = '0';   -- 24
    data_in <= X"24";
    wait until clk = '0';   -- 25
    data_in <= X"25";
    wait until clk = '0';   -- 26
    data_in <= X"26";
    wait until clk = '0';   -- 27
    data_in <= X"27";
    wait until clk = '0';   -- 28
    data_in <= X"28";
    wait until clk = '0';   -- 29
    data_in <= X"29";
    wait until clk = '0';   -- 2A
    data_in <= X"2A";
    wait until clk = '0';   -- 2B
    data_in <= X"2B";
    wait until clk = '0';   -- 2C
    data_in <= X"2C";
    wait until clk = '0';   -- 2D
    data_in <= X"2D";
    wait until clk = '0';   -- 2E
    data_in <= X"2E";
    wait until clk = '0';   -- 2F
    data_in <= X"2F";
    wait until clk = '0';   -- 30
    data_in <= X"30";
    wait until clk = '0';   -- 31
    data_in <= X"31";
    wait until clk = '0';   -- 32
    data_in <= X"32";
    wait until clk = '0';   -- 33
    data_in <= X"33";
    wait until clk = '0';   -- 34
    data_in <= X"34";
    wait until clk = '0';   -- 35
    data_in <= X"35";
    wait until clk = '0';   -- 36
    data_in <= X"36";
    wait until clk = '0';   -- 37
    data_in <= X"37";
    wait until clk = '0';   -- 38
    data_in <= X"38";
    wait until clk = '0';   -- 39
    data_in <= X"39";
    wait until clk = '0';   -- 3A
    data_in <= X"3A";
    wait until clk = '0';   -- 3B
    data_in <= X"3B";
    wait until clk = '0';   -- 3C
    data_in <= X"3C";
    wait until clk = '0';   -- 3D
    data_in <= X"3D";
    wait until clk = '0';   -- 3E
    data_in <= X"3E";
    wait until clk = '0';   -- 3F
    data_in <= X"3F";
 
 
 
    wait until clk = '0';   -- no write
    data_in <= X"FF";
 
    wait until clk = '0';   -- write and read on full, reads first out
    data_in <= X"EE";
    read <= '1';
 
    wait until clk = '0';   -- no read or write
    data_in <= X"AB";
    read <= '0';
    write <= '0';
 
 
-- read untill empty
 
    wait until clk = '0';
 
    read <= '1';
    for i in 0 to 61 loop   -- read out 62 more
        wait until clk = '0';
    end loop;
 
    read <= '0';
    wait until clk = '0';   --  dont read, 
 
    read <= '1';
    wait until clk = '0';   -- read last - 1 out
 
 
    read <= '0';
    wait until clk = '0';   --  dont read, 
 
    read <= '1';
    wait until clk = '0';   -- read last out
 
 
    read <= '0';    -- stop reading
 
                wait; -- will wait forever
        END PROCESS;
 
-- clock gen process
process
begin
    wait for 1 ns;
    clk <= '0';
    wait for 1 ns;
    clk <= '1';
end process;
 
 
 
END;

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Subversion Repositories srl_fifo

[/] [srl_fifo/] [trunk/] [rtl/] [tb_srl_fifo_64.vhd] - Blame information for rev 7

Line No.	Rev	Author	Line
1	4	amulcock	`----------------------------------------------------------------------------`
2			`---- ----`
3			`---- ----`
4			`---- This file is part of the srl_fifo project ----`
5			`---- http://www.opencores.org/cores/srl_fifo ----`
6			`---- ----`
7			`---- Description ----`
8			`---- Implementation of srl_fifo IP core according to ----`
9			`---- srl_fifo IP core specification document. ----`
10			`---- ----`
11			`---- To Do: ----`
12			`---- NA ----`
13			`---- ----`
14			`---- Author(s): ----`
15			`---- Andrew Mulcock, amulcock@opencores.org ----`
16			`---- ----`
17			`----------------------------------------------------------------------------`
18			`---- ----`
19			`---- Copyright (C) 2008 Authors and OPENCORES.ORG ----`
20			`---- ----`
21			`---- This source file may be used and distributed without ----`
22			`---- restriction provided that this copyright statement is not ----`
23			`---- removed from the file and that any derivative work contains ----`
24			`---- the original copyright notice and the associated disclaimer. ----`
25			`---- ----`
26			`---- This source file is free software; you can redistribute it ----`
27			`---- and/or modify it under the terms of the GNU Lesser General ----`
28			`---- Public License as published by the Free Software Foundation; ----`
29			`---- either version 2.1 of the License, or (at your option) any ----`
30			`---- later version. ----`
31			`---- ----`
32			`---- This source is distributed in the hope that it will be ----`
33			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
34			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
35			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
36			`---- details. ----`
37			`---- ----`
38			`---- You should have received a copy of the GNU Lesser General ----`
39			`---- Public License along with this source; if not, download it ----`
40			`---- from http://www.opencores.org/lgpl.shtml ----`
41			`---- ----`
42			`----------------------------------------------------------------------------`
43			`-- ----`
44			`-- CVS Revision History ----`
45			`-- ----`
46			`-- $Log: not supported by cvs2svn $ ----`
47			`-- ----`
48			`--`
49			`-- quick description`
50			`--`
51			`-- Based upon the using a shift register as a fifo which has been`
52			`-- around for years ( decades ), but really came of use to VHDL`
53			`-- when the Xilinx FPGA's started having SRL's.`
54			`--`
55			`-- In my view, the definitive article on shift register logic fifo's`
56			`-- comes from Mr Chapman at Xilinx, in the form of his BBFIFO`
57			`-- tecXeclusive article, which as at early 2008, Xilinx have`
58			`-- removed.`
59			`--`
60			`--`
61			`LIBRARY ieee;`
62			`USE ieee.std_logic_1164.ALL;`
63			`USE ieee.std_logic_unsigned.all;`
64			`USE ieee.numeric_std.ALL;`
65
66			`ENTITY tb_srl_fifo_64_vhd IS`
67			`END tb_srl_fifo_64_vhd;`
68
69			`ARCHITECTURE behavior OF tb_srl_fifo_64_vhd IS`
70
71			`constant width_tb : integer := 8;`
72
73			`-- Component Declaration for the Unit Under Test (UUT)`
74			`COMPONENT srl_fifo_64`
75			`GENERIC ( width : integer := width_tb ); -- set to how wide fifo is to be`
76			`PORT(`
77			`data_in : IN std_logic_vector(width_tb - 1 downto 0);`
78			`reset : IN std_logic;`
79			`write : IN std_logic;`
80			`read : IN std_logic;`
81			`clk : IN std_logic;`
82			`data_out : OUT std_logic_vector(width_tb -1 downto 0);`
83			`full : OUT std_logic;`
84			`half_full : OUT std_logic;`
85			`data_present : OUT std_logic`
86			`);`
87			`END COMPONENT;`
88
89			`--Inputs`
90			`SIGNAL reset : std_logic := '0';`
91			`SIGNAL write : std_logic := '0';`
92			`SIGNAL read : std_logic := '0';`
93			`SIGNAL clk : std_logic := '0';`
94			`SIGNAL data_in : std_logic_vector(width_tb - 1 downto 0) := (others=>'0');`
95
96			`--Outputs`
97			`SIGNAL data_out : std_logic_vector(width_tb -1 downto 0);`
98			`SIGNAL full : std_logic;`
99			`SIGNAL half_full : std_logic;`
100			`SIGNAL data_present : std_logic;`
101
102			`BEGIN`
103
104			`-- Instantiate the Unit Under Test (UUT)`
105			`uut: srl_fifo_64`
106			`GENERIC MAP (`
107			`width => width_tb`
108			`)`
109			`PORT MAP(`
110			`data_in => data_in,`
111			`data_out => data_out,`
112			`reset => reset,`
113			`write => write,`
114			`read => read,`
115			`full => full,`
116			`half_full => half_full,`
117			`data_present => data_present,`
118			`clk => clk`
119			`);`
120
121			`tb : PROCESS`
122			`BEGIN`
123
124
125
126			`-- Wait 100 ns for global reset to finish`
127			`wait for 100 ns;`
128
129			`wait until clk = '0';`
130			`reset <= '0';`
131
132			`-- Place stimulus here`
133
134			`wait until clk = '0'; -- 0`
135			`data_in <= X"AA";`
136			`write <= '1';`
137
138			`wait until clk = '0'; -- 1`
139			`data_in <= X"55";`
140
141			`wait until clk = '0'; -- 2`
142			`data_in <= X"02";`
143			`wait until clk = '0'; -- 3`
144			`data_in <= X"03";`
145			`wait until clk = '0'; -- 4`
146			`data_in <= X"04";`
147			`wait until clk = '0'; -- 5`
148			`data_in <= X"05";`
149			`wait until clk = '0'; -- 6`
150			`data_in <= X"06";`
151			`wait until clk = '0'; -- 7`
152			`data_in <= X"07";`
153			`wait until clk = '0'; -- 8`
154			`data_in <= X"08";`
155			`wait until clk = '0'; -- 9`
156			`data_in <= X"09";`
157			`wait until clk = '0'; -- A`
158			`data_in <= X"A0";`
159			`wait until clk = '0'; -- B`
160			`data_in <= X"B0";`
161			`wait until clk = '0'; -- C`
162			`data_in <= X"C0";`
163			`wait until clk = '0'; -- D`
164			`data_in <= X"D0";`
165			`wait until clk = '0'; -- E`
166			`data_in <= X"E0";`
167			`wait until clk = '0'; -- F`
168			`data_in <= X"F0";`
169			`wait until clk = '0'; -- 10`
170			`data_in <= X"10";`
171			`wait until clk = '0'; -- 11`
172			`data_in <= X"11";`
173			`wait until clk = '0'; -- 12`
174			`data_in <= X"12";`
175			`wait until clk = '0'; -- 13`
176			`data_in <= X"13";`
177			`wait until clk = '0'; -- 14`
178			`data_in <= X"14";`
179			`wait until clk = '0'; -- 15`
180			`data_in <= X"15";`
181			`wait until clk = '0'; -- 16`
182			`data_in <= X"16";`
183			`wait until clk = '0'; -- 17`
184			`data_in <= X"17";`
185			`wait until clk = '0'; -- 18`
186			`data_in <= X"18";`
187			`wait until clk = '0'; -- 19`
188			`data_in <= X"19";`
189			`wait until clk = '0'; -- 1A`
190			`data_in <= X"1A";`
191			`wait until clk = '0'; -- 1B`
192			`data_in <= X"1B";`
193			`wait until clk = '0'; -- 1C`
194			`data_in <= X"1C";`
195			`wait until clk = '0'; -- 1D`
196			`data_in <= X"1D";`
197			`wait until clk = '0'; -- 1E`
198			`data_in <= X"1E";`
199			`wait until clk = '0'; -- 1F`
200			`data_in <= X"1F";`
201
202			`--`
203
204			`wait until clk = '0'; -- 20`
205			`data_in <= X"20";`
206			`write <= '1';`
207
208			`wait until clk = '0'; -- 21`
209			`data_in <= X"21";`
210
211			`wait until clk = '0'; -- 22`
212			`data_in <= X"22";`
213			`wait until clk = '0'; -- 23`
214			`data_in <= X"23";`
215			`wait until clk = '0'; -- 24`
216			`data_in <= X"24";`
217			`wait until clk = '0'; -- 25`
218			`data_in <= X"25";`
219			`wait until clk = '0'; -- 26`
220			`data_in <= X"26";`
221			`wait until clk = '0'; -- 27`
222			`data_in <= X"27";`
223			`wait until clk = '0'; -- 28`
224			`data_in <= X"28";`
225			`wait until clk = '0'; -- 29`
226			`data_in <= X"29";`
227			`wait until clk = '0'; -- 2A`
228			`data_in <= X"2A";`
229			`wait until clk = '0'; -- 2B`
230			`data_in <= X"2B";`
231			`wait until clk = '0'; -- 2C`
232			`data_in <= X"2C";`
233			`wait until clk = '0'; -- 2D`
234			`data_in <= X"2D";`
235			`wait until clk = '0'; -- 2E`
236			`data_in <= X"2E";`
237			`wait until clk = '0'; -- 2F`
238			`data_in <= X"2F";`
239			`wait until clk = '0'; -- 30`
240			`data_in <= X"30";`
241			`wait until clk = '0'; -- 31`
242			`data_in <= X"31";`
243			`wait until clk = '0'; -- 32`
244			`data_in <= X"32";`
245			`wait until clk = '0'; -- 33`
246			`data_in <= X"33";`
247			`wait until clk = '0'; -- 34`
248			`data_in <= X"34";`
249			`wait until clk = '0'; -- 35`
250			`data_in <= X"35";`
251			`wait until clk = '0'; -- 36`
252			`data_in <= X"36";`
253			`wait until clk = '0'; -- 37`
254			`data_in <= X"37";`
255			`wait until clk = '0'; -- 38`
256			`data_in <= X"38";`
257			`wait until clk = '0'; -- 39`
258			`data_in <= X"39";`
259			`wait until clk = '0'; -- 3A`
260			`data_in <= X"3A";`
261			`wait until clk = '0'; -- 3B`
262			`data_in <= X"3B";`
263			`wait until clk = '0'; -- 3C`
264			`data_in <= X"3C";`
265			`wait until clk = '0'; -- 3D`
266			`data_in <= X"3D";`
267			`wait until clk = '0'; -- 3E`
268			`data_in <= X"3E";`
269			`wait until clk = '0'; -- 3F`
270			`data_in <= X"3F";`
271
272
273
274			`wait until clk = '0'; -- no write`
275			`data_in <= X"FF";`
276
277			`wait until clk = '0'; -- write and read on full, reads first out`
278			`data_in <= X"EE";`
279			`read <= '1';`
280
281			`wait until clk = '0'; -- no read or write`
282			`data_in <= X"AB";`
283			`read <= '0';`
284			`write <= '0';`
285
286
287			`-- read untill empty`
288
289			`wait until clk = '0';`
290
291			`read <= '1';`
292			`for i in 0 to 61 loop -- read out 62 more`
293			`wait until clk = '0';`
294			`end loop;`
295
296			`read <= '0';`
297			`wait until clk = '0'; -- dont read,`
298
299			`read <= '1';`
300			`wait until clk = '0'; -- read last - 1 out`
301
302
303			`read <= '0';`
304			`wait until clk = '0'; -- dont read,`
305
306			`read <= '1';`
307			`wait until clk = '0'; -- read last out`
308
309
310			`read <= '0'; -- stop reading`
311
312			`wait; -- will wait forever`
313			`END PROCESS;`
314
315			`-- clock gen process`
316			`process`
317			`begin`
318			`wait for 1 ns;`
319			`clk <= '0';`
320			`wait for 1 ns;`
321			`clk <= '1';`
322			`end process;`
323
324
325
326			`END;`