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[/] [ssbcc/] [trunk/] [core/] [9x8/] [build/] [uc/] [uc_combine_instr_ds.9x8] - Blame information for rev 2

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# Copyright 2013, Sinclair R.F., Inc.
# Test bench for synthesis tools:  combine INSTRUCTION and DATA_STACK
#
# Minimum Logic utilization
#   Xilinx      XC3S50A         N/A -- Spartan 3A doesn't support asynchronous reads
#   Xilinx      XC6SLX4         33 Slices, 111 Slice LUTs
 
ARCHITECTURE core/9x8 Verilog
 
INSTRUCTION     1024
DATA_STACK      16
RETURN_STACK    16
COMBINE         INSTRUCTION,DATA_STACK
 
OUTPORT 1-bit o_led O_LED
 
ASSEMBLY        uc_led.s

Line No.	Rev	Author	Line
1	2	sinclairrf	`# Copyright 2013, Sinclair R.F., Inc.`
2			`# Test bench for synthesis tools: combine INSTRUCTION and DATA_STACK`
3			`#`
4			`# Minimum Logic utilization`
5			`# Xilinx XC3S50A N/A -- Spartan 3A doesn't support asynchronous reads`
6			`# Xilinx XC6SLX4 33 Slices, 111 Slice LUTs`
7
8			`ARCHITECTURE core/9x8 Verilog`
9
10			`INSTRUCTION 1024`
11			`DATA_STACK 16`
12			`RETURN_STACK 16`
13			`COMBINE INSTRUCTION,DATA_STACK`
14
15			`OUTPORT 1-bit o_led O_LED`
16
17			`ASSEMBLY uc_led.s`

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[/] [ssbcc/] [trunk/] [core/] [9x8/] [build/] [uc/] [uc_combine_instr_ds.9x8] - Blame information for rev 2