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[/] [ssbcc/] [trunk/] [core/] [9x8/] [build/] [uc/] [uc_led.9x8] - Blame information for rev 2

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Line No. Rev Author Line
1 2 sinclairrf
# Copyright 2013, Sinclair R.F., Inc.
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# Test bench for synthesis tools:  simple LED flasher
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#
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# Performance
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#   Xilinx XC3S50A-4
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#     ISE-11.4   8.102 ns       123.4 MHz
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#     ISE-12.4   8.165 ns       122.5 MHz
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#     ISE-13.3   8.074 ns       123.3 MHz
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#     ISE-14.4   8.127 ns       123.0 MHz
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#   Xilinx XC3S50A-5
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#     ISE-11.4   6.757 ns       148.0 MHz
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#     ISE-12.4   6.771 ns       147.7 MHz
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#     ISE-13.3   6.744 ns       148.3 MHz
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#     ISE-14.4   6.773 ns       147.6 MHz
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#   Xilinx XC6SLX4L
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#     ISE-11.4   9.112 ns       109.7 MHz
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#     ISE-12.4   9.434 ns       106.0 MHz
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#     ISE-13.3   9.657 ns       103.6 MHz
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#     ISE-14.4   9.657 ns       103.6 MHz
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#   Xilinx XC6SLX4-2
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#     ISE-11.4   7.948 ns       125.8 MHz
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#     ISE-12.4   7.544 ns       132.6 MHz
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#     ISE-13.3   5.682 ns       176.0 MHz
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#     ISE-14.4   5.682 ns       176.0 MHz
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#   Xilinx XC6SLX4-3
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#     ISE-11.4   5.700 ns       175.4 MHz
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#     ISE-12.4   5.064 ns       197.5 MHz
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#     ISE-13.3   5.000 ns       200.0 MHz
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#     ISE-14.4   5.000 ns       200.0 MHz
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#
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# Minimum Logic utilization
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#   Xilinx      XC3S50A         130 Slices, 231 4-input LUTS
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#   Xilinx      XC6SLX4          35 Slices, 119 Slice LUTs
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ARCHITECTURE core/9x8 Verilog
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INSTRUCTION     1024
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RETURN_STACK    16
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DATA_STACK      16
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OUTPORT 1-bit o_led O_LED
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ASSEMBLY        uc_led.s

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