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# Copyright 2013, Sinclair R.F., Inc.

# Test bench for synthesis tools:  peripherals

#

# Performance

#   Xilinx XC3S50A-4

#     ISE-11.4  9.033 ns        110.7 MHz

#     ISE-12.4  8.667 ns        115.4 MHz

#     ISE-13.3  8.949 ns        111.7 MHz

#     ISE-14.4  8.768 ns        114.1 MHz

#   Xilinx XC3S50A-5

#     ISE-11.4  6.994 ns        143.0 MHz       (required 7.00 ns period)

#     ISE-12.4  7.085 ns        141.1 MHz       (required 6.95 ns period)

#     ISE-13.3  7.090 ns        141.0 MHz       (required 6.90 ns period)

#     ISE-14.4  7.068 ns        141.5 MHz       (required 6.90 ns period)

#

# Logic utilization (minimum resources)

#   Xilinx      XC3S50A         ISE 11.4        392 Slices, 713 4-input LUTs, 3 BRAMS

#                               ISE 12.4, 13.3, and 14.4 produce the same utilization

#   Xilinx      XC6SLX4         ISE 11.4        212 Slices, 508 Slice LUTs, 3 RAMB8BERs

#                               ISE 12.4        158 Slices, 463 Slice LUTs, 5 RAMB8BERs

#                               ISE 13.3        157 Slices, 432 Slice LUTs, 5 RAMB8BERs

#                               ISE 14.4        169 Slices, 413 Slice LUTs, 5 RAMB8BERs

ARCHITECTURE core/9x8 Verilog

INSTRUCTION     1024

RETURN_STACK    16

DATA_STACK      16

PARAMETER       G_CLK_FREQ_HZ   100_000_000

PERIPHERAL      adder_16bit

PERIPHERAL      latch           outport_latch=O_LATCH \

                                outport_addr=O_LATCH_ADDR \

                                inport=I_LATCH \

                                insignal=i_latch \

                                width=32

PERIPHERAL      latch           outport_latch=O_LATCH2 \

                                outport_addr=O_LATCH2_ADDR \

                                inport=I_LATCH2 \

                                insignal=i_latch2 \

                                width=23

PERIPHERAL      open_drain      inport=I_SDA \

                                outport=O_SDA \

                                iosignal=io_sda

PERIPHERAL      open_drain      inport=I_SCL \

                                outport=O_SCL \

                                iosignal=io_scl

PERIPHERAL      PWM_8bit        outport=O_PWM \

                                outsignal=o_pwm \

                                ratemethod=G_CLK_FREQ_HZ/60_000

PERIPHERAL      PWM_8bit        outport=O_PWM2 \

                                outsignal=o_pwm2 \

                                ratemethod=G_CLK_FREQ_HZ/30_000 \

                                instances=3 \

                                norunt

PERIPHERAL      timer           inport=I_TIMER \

                                ratemethod=G_CLK_FREQ_HZ/1_000

PERIPHERAL      UART            inport=I_UART1_RX \

                                outport=O_UART1_TX \

                                inempty=I_UART1_INEMPTY \

                                outstatus=I_UART1_OUTSTATUS \

                                baudmethod=G_CLK_FREQ_HZ/115200

PERIPHERAL      UART            inport=I_UART2_RX \

                                outport=O_UART2_TX \

                                inempty=I_UART2_INEMPTY \

                                outstatus=I_UART2_OUTSTATUS \

                                baudmethod=G_CLK_FREQ_HZ/115200 \

                                insignal=i_uart2_rx \

                                outsignal=o_uart2_tx \

                                inFIFO=16 \

                                outFIFO=16

ASSEMBLY        uc_dummy.s