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sinclairrf |
<!-- Copyright 2012, Sinclair R.F., Inc. -->
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<html>
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<title>
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9-bit opcode, 8-bit data stack-based micro controller
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</title>
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<body>
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<b>9-bit Opcode, 8-bit Data, Stack-Based Micro Controller</b><br/>
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Copyright 2012, Sinclair R.F., Inc.<br/><br/>
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This document describes the 9-bit opcode, 8-bit data, stack-based
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microcontroller.
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<h1>Contents</h1>
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<b><a href="opcodes.html">Opcodes</a></b><br/>
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<b><a href="macros.html">Macros</a></b><br/>
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<h1>Directory Contents</h1>
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This directory contains the assembler and the Verilog and VHDL templates for
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the processor. While the assember can be run by itself, it is more
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typically run within the "<tt>../../ssbcc</tt>" script as part of making a
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compute computer core.<br/><br/>
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The "<tt>core.v</tt>" and "<tt>core.vhd</tt>" files in this directory are not
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complete modules. They cannot be compiled.<br/><br/>
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<h1>Introduction</h1>
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This processor is a minimalist FPGA-based microcontroller. It provides
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8-bit data manipulation operations and function calls. There are no
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condition registers as the results of tests are on the data stack. The
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instruction space, data stack size, return stack size, and existence and
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sizes of RAMs and ROMs are controlled by a configuration file so that the
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processor can be sized for the problem at hand. The configuration file also
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describes the input and output ports and include 0 to 8 bit port
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widths and strobes. A complete processor can be implemented using just
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the configuration file and the assembly file.<br/><br/>
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A 9-bit opcode was chosen because (1) it works well with Altera,
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Lattice, and Xilinx SRAM widths and (2) it allows pushing 8-bit data
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onto the stack with a single instruction.<br/><br/>
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An 8-bit data width was chosen because that's a practical minimal
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size. It is also common to many hardware interfaces such as I2C
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devices.<br/><br/>
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The machine has single-cycle instruction execution for all
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instructions. However, some operations, such as a jump, require pushing the
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8 lsb of the target address onto the stack in one instruction, executing the
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jump with the remaining 5 msb of the target address, and then a <tt>nop</tt>
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during the following instruction.<br/><br/>
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Only one data stack shift can be achieved per instruction cycle. This means
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that all operations that consume the top two elements of the stack, such as
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a store instruction, can only remove one element from the stack and must be
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immediately followed by a "<tt>drop</tt>" instruction to remove what had
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been the second element on the data stack.<br/><br/>
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This architecture accommodates up to a 13-bit instruction address space by
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first pushing the 8 least significant bits of the destination address onto
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the stack and then encoding the 5 most significant bits in the jump
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instruction. This is the largest practicable instruction address width
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because (1) one bit of the opcode is required to indicate pushing an
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8-bit value onto the stack, (2) one bit of the remaining 8 bits is
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required to indicate a jump instructions, (3) one bit is required to
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indicate whether the jump is always performed or is conditionally performed,
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and (4) one more bit is required to indicate whether the jump is a jump
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or a call. This consumes 4 bits and leaves 5 bits of additional
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address space for the jump instruction.<br/><br/>
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This architecture also supports 0 to 4 pages of RAM and ROM with a
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combined limit of 4 pages. Each page of RAM or ROM can hold up to
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256 bytes of data. This architecture provides up to 1 kB of
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RAM and ROM for the micro controller.<br/><br/>
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<h1>Design</h1>
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The processor is a mix of instructions that operate on the top element of the
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data stack (such as left or right shifts); operations that combine the top
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two elements of the data stack such as addition and subtraction and bit wise
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logical operations; operations that manipulate the data stack such as
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<tt>drop</tt>, <tt>nip</tt>, and 8-bit pushes; operations that move data
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between the data stack and the return stack; jumps and calls and their
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conditional variants; memory operations; and I/O operations.<br/><br/>
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This section describes these. The next section defines these instructions in
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detail.<br/><br/>
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<ul>
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<li>Data Stack Operations:<br/><br/>
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The data stack is an 8 bit wide stack. The top two elements of this
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data stack, called <tt>T</tt> for the top of the data stack and
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<tt>N</tt> for the next-to-top of the data stack, are stored in
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registers so that they are immediately available to the processor core.
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The remaining values are stored in the 8-bit wide RAM
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comprising the stack. This will usually be some form of distributed RAM
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on an FPGA. The index to the top of the stack is retained in a
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register.<br/><br/>
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A couple of examples illustrate how the data stack is
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manipulated:<br/><br/>
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<ul>
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<li>A push instruction moves <tt>N</tt> onto the data stack RAM and
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increments the pointer into the data stack, moves <tt>T</tt> into
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<tt>N</tt>, and replaces <tt>T</tt> with the value being pushed onto
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the data stack.<br/><br/>
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<li>The <tt><<0</tt> instruction rotates the value in <tt>T</tt>
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left one bit and brings a zero in as the new lsb. The data stack is
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otherwise left unchanged.<br/><br/>
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<li>The <tt>swap</tt> instruction swaps the values in <tt>T</tt> and
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<tt>N</tt> and leaves the rest of the data stack unchanged.<br/><br/>
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<li>The <tt>drop</tt> instruction moves <tt>N</tt> into <tt>T</tt>, the
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top of the data stack RAM into <tt>N</tt>, and decrements the pointer
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into the data stack.<br/><br/>
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<li>The <tt>store</tt> instruction requires the value to be stored and
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the address to which it is to be stored. Since the address cannot be
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encoded as part of the <tt>store</tt> instruction and since multi-byte
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<tt>store+</tt> and <tt>store-</tt> instructions require the address
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to remain on the stack as the rest of the stack is consumed, the
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address for the <tt>store</tt> instruction is in <tt>T</tt> while the
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data to be stored is in <tt>N</tt>. I.e., if the value to be stored
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is in <tt>T</tt>, then the address where it is to be stored is then
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pushed onto the data stack and the <tt>store</tt> instruction is
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issued. The <tt>store</tt> instruction drops the top of the data
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stack, leaving the value that was stored on the top of the data stack.
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The <tt>store+</tt> and <tt>store-</tt> instruction differ from this
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in that the value in <tt>N</tt> is dropped from the data stack and the
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altered address is retained in <tt>T</tt>.<br/><br/>
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<li>The <tt>outport</tt> instruction is similar to the <tt>store</tt>
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instruction in that the port number is pushed onto the data stack
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prior to the <tt>outport</tt> instruction which then drops the port
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number from the data stack.<br/><br/>
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</ul>
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The return stack is similar except that only the top-most value,
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<tt>R</tt>, is retained in a dedicated register.<br/><br/>
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Separate registers are used for <tt>N</tt> and the top of the return stack
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are implmented in registers rather than the output of the RAM because
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there there are multipler sources for their values when they are added
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to their stack. Instead, the value registered in <tt>N</tt> or
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<tt>R</tt> is pushed onto the body of the stack.<br/><br/>
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Faster stack implementations won't improve the processor speed because the
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3 levels of logic required to implement the core are slower than
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the storing <tt>N</tt> or <tt>R</tt> into their stack bodies.<br/><br/>
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</li>
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<li>Jump and Call Instructions:<br/><br/>
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The large SRAM on the FPGAs can have registers for their input addresses
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and registers for their output data. These registers are used to extract
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the fastest speed possible from the memory. While it is possible to
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design the processor ROM to avoid these registers, that isn't always
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what's desired. This however impacts how jump instructions are
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performed.<br/><br/>
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Specifically, if a jump instruction changes the program counter during
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cycle <em>n</em>, then the new input address is registered at the end of that
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clock cycle and the corresponding data is registered at the end of the
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next clock cycle, i.e., the new opcode is available at the end of cycle
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<em>n</em>+1. That is, the new opcode can't performed by the core until
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cycle <em>n</em>+2.<br/><br/>
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This means that the instruction immediately following a jump or call
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instruction will be performed before the first instruction at the target
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of the jump or call. For an unconditional jump or call, i.e.,
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<tt>jump</tt> or <tt>call</tt>, this subsequent instruction will
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normally be a <tt>nop</tt>. However, for a conditional jump or call,
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i.e., a <tt>jumpc</tt> or <tt>callc</tt> instruction, this will normally
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be a <tt>drop</tt> that eliminates the conditional used to determine
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whether or not the branch was taken.<br/><br/>
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Some examples are:<br/><br/>
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<ul>
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<li>The following block shows a conditional jump and an unconditional
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jump being used for an
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"<tt>if ... else .. endif</tt>" block.
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The <tt>.jump</tt> and <tt>.jumpc</tt> macros are used to encode
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pushing the 8 lsb of the target address onto the stack and to
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encode the 5 msb into the <tt>jump</tt> or <tt>jumpc</tt>
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instruction. The macros also add the subsequent <tt>nop</tt> and
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<tt>drop</tt> respectively.<br/><br/>
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<tt>
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; determine which value to put on the stack based on the value in T<br/>
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; ( f - u )<br/>
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.jumpc(true_case)<br/>
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0x80 .jump(end_case)<br/>
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:true_case<br/>
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0x37<br/>
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:end_case
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</tt><br/><br/>
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The condition on the top of the data stack is consumed by the initial
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<tt>jumpc</tt>. If <tt>T</tt> is true then <tt>0x37</tt> will be
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pushed onto the data stack. Otherwise <tt>0x80</tt> will be pushed
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onto the data stack. This can be written slightly more efficienty by
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replacing the <tt>nop</tt> in the <tt>.jump</tt> macro as
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follows:<br/><br/>
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<tt> .jumpc(true_case) .jump(end_case,0x37) :true_case 0x37 :end_case</tt><br/><br/>
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This reduces the total number of instructions from 8
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to 7.<br/><br/>
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</li>
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<li>The following statement shows how a function can return a flag used
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by a second conditional call:<br/><br/>
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<tt> .call(data_pending) .callc(process_data)</tt><br/><br/>
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Here, the <tt>data_pending</tt> function returns a true or false
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flag on the top of the data stack. The subsequent <tt>callc</tt> then
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processes the data only if there was data to process.<br/><br/>
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</ul>
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</li>
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<li><a name="memory">Memory Operations</a>:<br/><br/>
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The fetch and store memory access instructions are designed such that four
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banks of memory can be accessed, each of which can hold up to
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256 bytes. This allows up to a total of 1 kB of
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memory to be accessed by the processor.<br/><br/>
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There are three variants of the fetch instruction and three variants of
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the store instruction.<br/><br/>
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The simplest fetch instruction exchanges the top of the data stack with
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the value it had indexed from the memory bank encoded in the store
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instruction. For example, the two instruction sequence<br/><br/>
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<tt> 0x10 .fetch(0)</tt><br/><br/>
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has the effect of pushing the value from <tt>00_0001_0000</tt> onto the
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data stack where the leading two zeros are the bank number.<br/><br/>
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The simplest store instruction similarly uses the top of the data stack as
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the address within the memory bank and stores the value in the
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next-to-top of the data stack at that location. For example, the four
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instruction sequence<br/><br/>
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<tt> 0x5A 0x10 .store(0) drop</tt><br/><br/>
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has the effect of storing the value <tt>0x5A</tt> in the memory address
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<tt>00_0001_0000</tt>.<br/><br/>
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The remaining two fetch and two store instructions are designed to
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facilitate storing and fetching multi-byte values. These vectorized
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fetch and store instructions increment or decrement the top of the stack
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while reading from or storing to memory. For example, the instruction
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sequence<br/><br/>
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<tt> 0x13 .fetch-(0) .fetch-(0) .fetch-(0) .fetch(0)</tt><br/><br/>
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will push the memory values from <tt>00_0001_0011</tt>,
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<tt>00_0001_0010</tt>, <tt>00_0001_0001</tt>, and <tt>00_0001_0000</tt>
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onto the data stack with the value from <tt>00_0001_0000</tt> on the
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top of the stack. The instruction sequence<br/><br/>
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<tt> 0x10 .store+(0) .store+(0) .store+(0) .store(0) drop</tt><br/><br/>
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has the reverse effect in that it stores the top four values on the
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stack in memory with the value that had been at the top of the stack
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being stored at address <tt>00_0001_000</tt>. That is, it has the
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effect of storing the values from the four-fetch instruction sequence
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into memory and preserving their order.<br/><br/>
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If the values were in the reverse order on the stack the instruction
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sequence would have been<br/><br/>
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<tt> 0x13 .store-(0) .store-(0) .store-(0) .store-(0) drop</tt><br/><br/>
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In practice, the <tt>.fetch</tt> and <tt>.store</tt> macros do not use a
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hard-wired number for the bank address. Instead the memory bank is
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specified by a symbolic name. For example, a memory is defined in the
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micro controller architecture file using a statement such as:<br/><br/>
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<tt> MEMORY RAM ram 32</tt><br/><br/>
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which defines a RAM named "<tt>ram</tt>" and allocates 32 bytes of
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storage. The corresponding RAM in the assembler code is then selected by
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the directive:<br/><br/>
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<tt> .memory RAM ram</tt><br/><br/>
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and variables within this bank of memory are defined using the
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"<tt>.variable</tt>" directive as follows:<br/><br/>
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<tt> .variable single_value 0<br/>
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.variable multi_count  2*0</tt><br/><br/>
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The first of these defines "<tt>single_value</tt>" to be a single-byte
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value initialized to zero and the second defines "<tt>multi_count</tt>"
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to be a two byte value initialized to 0. Variable order is
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preserved by the assembler.<br/><br/>
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As an example, the following assembly code will initialize this block of
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memory to zero:<br/><br/>
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<tt> $(size['ram']) :loop 0 swap .store-(ram) .jumpc(loop,nop) drop</tt><br/><br/>
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Note that the memory size is not hard-wired into the
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assembly code but is accessed through the calculation
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"<tt>$(size['ram'])</tt>". Also, since the <tt>.store-</tt> macro
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decrements the top of the stack before the conditional jump, the last
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value stored in memory before the loop exits will have been stored at
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address <tt>0x01</tt>. However, since the size must be a power of
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two, the first value stored will be at the effective
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address <tt>0x00</tt>. The loop itself is 6 instructions.
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This can be reduced to 5 instructions at the cost of an additional
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drop instruction as follows:<br/><br/>
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<tt> $(size['ram']) 0 :loop swap .store-(ram) .jumpc(loop,0) drop drop</tt><br/><br/>
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The optional argument to the <tt>.jumpc</tt> macro is required so that
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the memory address is not dropped from the data stack after the
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conditional is tested. The equivalent operation without replacing the
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<tt>drop</tt> instruction with a <tt>nop</tt> instruction would be:<br/><br/>
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<tt> $(size['ram']) :loop 0 swap .store-(ram) dup .jumpc(loop,drop) drop</tt><br/><br/>
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where the <tt>drop</tt> has been explicitely included.<br/><br/>
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Memories can be either "<tt>RAM</tt>" or "<tt>ROM</tt>" and must be
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|
|
declared as the same type in the architecture file and in the assembler
|
| 263 |
|
|
files. Within the assembler source the "<tt>.memory</tt>" directive can
|
| 264 |
|
|
be repeated so that variables in one memory bank can be defined in
|
| 265 |
|
|
multiple assembler files. The "<tt>.memory</tt>" directive must be
|
| 266 |
|
|
repeated if the source file changes and after function
|
| 267 |
|
|
definitions.<br/><br/>
|
| 268 |
|
|
The Forth language requires that the MSB of multi-word values be stored on
|
| 269 |
|
|
the top of the data stack. Using the <tt>.store+</tt> and
|
| 270 |
|
|
<tt>.fetch-</tt> instructions to write to and read from memory will
|
| 271 |
|
|
keep the corresponding MSB at the top of the stack and as the first byte
|
| 272 |
|
|
in memory. If the LSB is at the top of the data stack then the
|
| 273 |
|
|
<tt>.store-</tt> instruction can be used to store it in the desired
|
| 274 |
|
|
order.<br/><br/>
|
| 275 |
|
|
The following macros are provided to facilitate memory
|
| 276 |
|
|
operations:<br/><br/>
|
| 277 |
|
|
<ul>
|
| 278 |
|
|
<li><tt>.fetch(name)</tt> where <tt>name</tt> is the name of a
|
| 279 |
|
|
RAM<br/><br/>
|
| 280 |
|
|
This generates the single-instruction <tt>fetch</tt> opcode with the
|
| 281 |
|
|
memory bank number encoded in the instruction.<br/><br/>
|
| 282 |
|
|
<li><tt>.fetch+(name)</tt> where <tt>name</tt> is the name of a
|
| 283 |
|
|
RAM<br/><br/>
|
| 284 |
|
|
This generates the single-instruction <tt>fetch+</tt> opcode with the
|
| 285 |
|
|
memory bank number encoded in the instruction.<br/><br/>
|
| 286 |
|
|
<li><tt>.fetch-(name)</tt> where <tt>name</tt> is the name of a
|
| 287 |
|
|
RAM<br/><br/>
|
| 288 |
|
|
This generates the single-instruction <tt>fetch-</tt> opcode with the
|
| 289 |
|
|
memory bank number encoded in the instruction.<br/><br/>
|
| 290 |
|
|
<li><tt>.fetchindexed(name)</tt> where <tt>name</tt> is a variable
|
| 291 |
|
|
name<br/><br/>
|
| 292 |
|
|
If <tt>variable</tt> is in memory <tt>ram</tt> then
|
| 293 |
|
|
<tt>.fetchindexed(variable)</tt> becomes the 3 instruction
|
| 294 |
|
|
sequence
|
| 295 |
|
|
"<tt>variable + .fetch(ram)</tt>"<br/><br/>
|
| 296 |
|
|
<li><tt>.fetchvalue(name)</tt> where <tt>name</tt> is a variable
|
| 297 |
|
|
name.<br/><br/>
|
| 298 |
|
|
If <tt>variable</tt> is in memory <tt>ram</tt> then
|
| 299 |
|
|
<tt>.fetchvalue(variable)</tt> becomes the 2 instruction
|
| 300 |
|
|
sequence "<tt>variable .fetch(ram)</tt>"<br/><br/>
|
| 301 |
|
|
<li><tt>.fetchvector(name,length)</tt><br/><br/>
|
| 302 |
|
|
<tt>name</tt> is a variable name<br/>
|
| 303 |
|
|
<tt>length</tt> is the length of the vector to transfer from the data
|
| 304 |
|
|
stack to the RAM.<br/><br/>
|
| 305 |
|
|
If <tt>variable</tt> is in memory <tt>ram</tt> then
|
| 306 |
|
|
<tt>.fetchvector(variable,4)</tt> becomes the 5 instruction
|
| 307 |
|
|
sequence
|
| 308 |
|
|
"<tt>$(variable+3) .fetch-(ram) .fetch-(ram) .fetch-(ram) .fetch(ram)</tt>"<br/><br/>
|
| 309 |
|
|
<li><tt>.store(name)</tt> where <tt>name</tt> is the name of a
|
| 310 |
|
|
RAM<br/><br/>
|
| 311 |
|
|
This generates the single-instruction <tt>store</tt> opcode with the
|
| 312 |
|
|
memory bank number encoded in the instruction.<br/><br/>
|
| 313 |
|
|
<li><tt>.store+(name)</tt> where <tt>name</tt> is the name of a
|
| 314 |
|
|
RAM<br/><br/>
|
| 315 |
|
|
This generates the single-instruction <tt>store+</tt> opcode with the
|
| 316 |
|
|
memory bank number encoded in the instruction.<br/><br/>
|
| 317 |
|
|
<li><tt>.store-(name)</tt> where <tt>name</tt> is the name of a
|
| 318 |
|
|
RAM<br/><br/>
|
| 319 |
|
|
This generates the single-instruction <tt>store-</tt> opcode with the
|
| 320 |
|
|
memory bank number encoded in the instruction.<br/><br/>
|
| 321 |
|
|
<li><tt>.storeindexed(name)</tt><br/><br/>
|
| 322 |
|
|
<tt>name</tt> is a variable name<br/>
|
| 323 |
|
|
An optional second argument can replace the <tt>drop</tt> that normally
|
| 324 |
|
|
ends this sequence.<br/><br/>
|
| 325 |
|
|
If <tt>variable</tt> is in memory <tt>ram</tt> then
|
| 326 |
|
|
<tt>.storeindexed(variable)</tt> becomes the 4 instruction
|
| 327 |
|
|
sequence
|
| 328 |
|
|
"<tt>variable + .store(ram) drop</tt>"<br/><br/>
|
| 329 |
|
|
<li><tt>.storevalue(name)</tt> where <tt>name</tt> is a variable
|
| 330 |
|
|
name.<br/><br/>
|
| 331 |
|
|
An optional second argument can replace the <tt>drop</tt> that normally
|
| 332 |
|
|
ends this sequence.<br/><br/>
|
| 333 |
|
|
If <tt>variable</tt> is in memory <tt>ram</tt> then
|
| 334 |
|
|
<tt>.storevalue(variable)</tt> becomes the 3 instruction
|
| 335 |
|
|
sequence "<tt>variable .store(ram) drop</tt>"<br/><br/>
|
| 336 |
|
|
<li><tt>.storevector(name,length)</tt><br/><br/>
|
| 337 |
|
|
<tt>name</tt> is a variable name<br/>
|
| 338 |
|
|
<tt>length</tt> is the length of the vector to transfer from the data
|
| 339 |
|
|
stack to the RAM.<br/><br/>
|
| 340 |
|
|
If <tt>variable</tt> is in memory <tt>ram</tt> then
|
| 341 |
|
|
<tt>.storevector(variable,4)</tt> becomes the 6 instruction
|
| 342 |
|
|
sequence
|
| 343 |
|
|
"<tt>variable .store+(ram) .store+(ram) .store+(ram) .store(ram) drop</tt>"<br/><br/>
|
| 344 |
|
|
</ul>
|
| 345 |
|
|
</ul>
|
| 346 |
|
|
<h1>OPCODES</h1>
|
| 347 |
|
|
This section documents the opcodes.<br/><br/>
|
| 348 |
|
|
Alphabetic listing:
|
| 349 |
|
|
<a href="#&">&</a>,
|
| 350 |
|
|
<a href="#+">+</a>,
|
| 351 |
|
|
<a href="#-">-</a>,
|
| 352 |
|
|
<a href="#-1<>">-1<></a>,
|
| 353 |
|
|
<a href="#-1=">-1=</a>,
|
| 354 |
|
|
<a href="#0<>">0<></a>,
|
| 355 |
|
|
<a href="#0=">0=</a>,
|
| 356 |
|
|
<a href="#0>>">0>></a>,
|
| 357 |
|
|
<a href="#1+">1+></a>,
|
| 358 |
|
|
<a href="#1-">1-></a>,
|
| 359 |
|
|
<a href="#1>>">1>></a>,
|
| 360 |
|
|
<a href="#<<0"><<0</a>,
|
| 361 |
|
|
<a href="#<<1"><<1</a>,
|
| 362 |
|
|
<a href="#<<msb"><<msb</a>,
|
| 363 |
|
|
<a href="#>r">>r</a>,
|
| 364 |
|
|
<a href="#FE=">FE=</a>,
|
| 365 |
|
|
<a href="#FF=">FF=</a>,
|
| 366 |
|
|
<a href="#^">^</a>,
|
| 367 |
|
|
<a href="#call">call</a>,
|
| 368 |
|
|
<a href="#callc">callc</a>,
|
| 369 |
|
|
<a href="#dis">dis</a>,
|
| 370 |
|
|
<a href="#drop">drop</a>,
|
| 371 |
|
|
<a href="#dup">dup</a>,
|
| 372 |
|
|
<a href="#ena">ena</a>,
|
| 373 |
|
|
<a href="#fetch">fetch</a>,
|
| 374 |
|
|
<a href="#fetch+">fetch+</a>,
|
| 375 |
|
|
<a href="#fetch-">fetch-</a>,
|
| 376 |
|
|
<a href="#inport">inport</a>,
|
| 377 |
|
|
<a href="#jump">jump</a>,
|
| 378 |
|
|
<a href="#jumpc">jumpc</a>,
|
| 379 |
|
|
<a href="#lsb>>">lsb>></a>,
|
| 380 |
|
|
<a href="#msb>>">msb>></a>,
|
| 381 |
|
|
<a href="#nip">nip</a>,
|
| 382 |
|
|
<a href="#nop">nop</a>,
|
| 383 |
|
|
<a href="#or">or</a>,
|
| 384 |
|
|
<a href="#outport">outport</a>,
|
| 385 |
|
|
<a href="#over">over</a>,
|
| 386 |
|
|
<a href="#push">push</a>,
|
| 387 |
|
|
<a href="#r>">r></a>,
|
| 388 |
|
|
<a href="#r@">r@</a>,
|
| 389 |
|
|
<a href="#return">return</a>,
|
| 390 |
|
|
<a href="#store">store</a>,
|
| 391 |
|
|
<a href="#store+">store+</a>,
|
| 392 |
|
|
<a href="#store-">store-</a>,
|
| 393 |
|
|
<a href="#swap">swap</a>
|
| 394 |
|
|
<br/><br/>
|
| 395 |
|
|
<h2><a name="opcode_mapping">Opcode Mapping</a></h2>
|
| 396 |
|
|
<table>
|
| 397 |
|
|
<tr>
|
| 398 |
|
|
<th align="left">Opcode </th>
|
| 399 |
|
|
<th>8</th><th>7</th><th>6</th><th>5</th><th>4</th><th>3 </th><th>2</th><th>1</th><th>0 </th>
|
| 400 |
|
|
<th align="left">Description</th>
|
| 401 |
|
|
</tr>
|
| 402 |
|
|
<th align="left"><a href="#nop">nop</a></th>
|
| 403 |
|
|
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
|
| 404 |
|
|
<td align="left">no operation</td>
|
| 405 |
|
|
</tr>
|
| 406 |
|
|
<th align="left"><a href="#<<0"><<0</a></th>
|
| 407 |
|
|
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td>
|
| 408 |
|
|
<td align="left">left shift 1 bit and bring in a 0</td>
|
| 409 |
|
|
</tr>
|
| 410 |
|
|
<th align="left"><a href="#<<1"><<1</a></th>
|
| 411 |
|
|
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td>
|
| 412 |
|
|
<td align="left">left shift 1 bit and bring in a 1</td>
|
| 413 |
|
|
</tr>
|
| 414 |
|
|
<th align="left"><a href="#<<msb"><<msb</a></th>
|
| 415 |
|
|
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td>
|
| 416 |
|
|
<td align="left">left shift 1 bit and rotate the msb into the lsb</td>
|
| 417 |
|
|
</tr>
|
| 418 |
|
|
<th align="left"><a href="#0>>">0>></a></th>
|
| 419 |
|
|
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td>
|
| 420 |
|
|
<td align="left">right shift 1 bit and bring in a 0</td>
|
| 421 |
|
|
</tr>
|
| 422 |
|
|
<th align="left"><a href="#1>>">1>></a></th>
|
| 423 |
|
|
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td>
|
| 424 |
|
|
<td align="left">right shift 1 bit and bring in a 1</td>
|
| 425 |
|
|
</tr>
|
| 426 |
|
|
<th align="left"><a href="#msb>>">msb>></a></th>
|
| 427 |
|
|
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td>
|
| 428 |
|
|
<td align="left">right shift 1 bit and keep the msb the same</td>
|
| 429 |
|
|
</tr>
|
| 430 |
|
|
<th align="left"><a href="#lsb>>">lsb>></a></th>
|
| 431 |
|
|
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td>
|
| 432 |
|
|
<td align="left">right shift 1 bit and rotate the lsb into the msb</td>
|
| 433 |
|
|
</tr>
|
| 434 |
|
|
<th align="left"><a href="#dup">dup</a></th>
|
| 435 |
|
|
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td>
|
| 436 |
|
|
<td align="left">push a duplicate of the top of the data stack onto the data stack</td>
|
| 437 |
|
|
</tr>
|
| 438 |
|
|
<th align="left"><a href="#r@">r@</a></th>
|
| 439 |
|
|
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td>
|
| 440 |
|
|
<td align="left">push a duplicate of the top of the return stack onto the data stack</td>
|
| 441 |
|
|
</tr>
|
| 442 |
|
|
<th align="left"><a href="#over">over</a></th>
|
| 443 |
|
|
<td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td>
|
| 444 |
|
|
<td align="left">push a duplicate of the next-to-top of the data stack onto the data stack</td>
|
| 445 |
|
|
</tr>
|
| 446 |
|
|
<th align="left"><a href="#swap">swap</a></th>
|
| 447 |
|
|
<td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td>
|
| 448 |
|
|
<td align="left">swap the top and the next-to-top of the data stack</td>
|
| 449 |
|
|
</tr>
|
| 450 |
|
|
<th align="left"><a href="#+">+</a></th>
|
| 451 |
|
|
<td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td>
|
| 452 |
|
|
<td align="left">pop the stack and replace the top with N+T</td>
|
| 453 |
|
|
</tr>
|
| 454 |
|
|
<th align="left"><a href="#-">-</a></th>
|
| 455 |
|
|
<td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td>
|
| 456 |
|
|
<td align="left">pop the stack and replace the top with N-T</td>
|
| 457 |
|
|
</tr>
|
| 458 |
|
|
<th align="left"><a href="#dis">dis</a></th>
|
| 459 |
|
|
<td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td>
|
| 460 |
|
|
<td align="left">disable interrupts</td>
|
| 461 |
|
|
</tr>
|
| 462 |
|
|
<th align="left"><a href="#ena">ena</a></th>
|
| 463 |
|
|
<td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td>
|
| 464 |
|
|
<td align="left">enable interrupts</td>
|
| 465 |
|
|
</tr>
|
| 466 |
|
|
<th align="left"><a href="#0=">0=</a></th>
|
| 467 |
|
|
<td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
|
| 468 |
|
|
<td align="left">replace the top of the stack with "<tt>0xFF</tt>" if it is "<tt>0x00</tt>" (i.e., it is zero), otherwise replace it with "<tt>0x00</tt>"<br/>
|
| 469 |
|
|
</tr>
|
| 470 |
|
|
<th align="left"><a href="#0<>">0<></a></th>
|
| 471 |
|
|
<td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td>
|
| 472 |
|
|
<td align="left">replace the top of the stack with "<tt>0xFF</tt>" if it is not "<tt>0x00</tt>" (i.e., it is non-zero), otherwise replace it with "<tt>0x00</tt>"<br/>
|
| 473 |
|
|
</tr>
|
| 474 |
|
|
<th align="left"><a href="#-1=">-1=</a></th>
|
| 475 |
|
|
<td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td>
|
| 476 |
|
|
<td align="left">replace the top of the stack with "<tt>0xFF</tt>" if it is "<tt>0xFF</tt>" (i.e., it is all ones), otherwise replace it with "<tt>0x00</tt>"<br/>
|
| 477 |
|
|
</tr>
|
| 478 |
|
|
<th align="left"><a href="#-1<>">-1<></a></th>
|
| 479 |
|
|
<td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td>
|
| 480 |
|
|
<td align="left">replace the top of the stack with "<tt>0xFF</tt>" if it is not "<tt>0xFF</tt>" (i.e., it is not all ones), otherwise replace it with "<tt>0x00</tt>"<br/>
|
| 481 |
|
|
</tr>
|
| 482 |
|
|
<th align="left"><a href="#return">return</a></th>
|
| 483 |
|
|
<td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td>
|
| 484 |
|
|
<td align="left">return from a function call</td>
|
| 485 |
|
|
</tr>
|
| 486 |
|
|
<th align="left"><a href="#inport">inport</a></th>
|
| 487 |
|
|
<td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td>
|
| 488 |
|
|
<td align="left">replace the top of the stack with the contents of the specified input port</td>
|
| 489 |
|
|
</tr>
|
| 490 |
|
|
<th align="left"><a href="#outport">outport</a></th>
|
| 491 |
|
|
<td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td>
|
| 492 |
|
|
<td align="left">write the next-to-top of the data stack to the output port specified by the top of the data stack</td>
|
| 493 |
|
|
</tr>
|
| 494 |
|
|
<th align="left"><a href="#>r">>r</a></th>
|
| 495 |
|
|
<td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td>
|
| 496 |
|
|
<td align="left">Pop the top of the data stack and push it onto the return stack</td>
|
| 497 |
|
|
</tr>
|
| 498 |
|
|
<th align="left"><a href="#r>">r></a></th>
|
| 499 |
|
|
<td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td>
|
| 500 |
|
|
<td align="left">Pop the top of the return stack and push it onto the data stack</td>
|
| 501 |
|
|
</tr>
|
| 502 |
|
|
<th align="left"><a href="#&">&</a></th>
|
| 503 |
|
|
<td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td>
|
| 504 |
|
|
<td align="left">pop the stack and replace the top with N & T</td>
|
| 505 |
|
|
</tr>
|
| 506 |
|
|
<th align="left"><a href="#or">or</a></th>
|
| 507 |
|
|
<td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td>
|
| 508 |
|
|
<td align="left">pop the stack and replace the top with N | T</td>
|
| 509 |
|
|
</tr>
|
| 510 |
|
|
<th align="left"><a href="#^">^</a></th>
|
| 511 |
|
|
<td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td>
|
| 512 |
|
|
<td align="left">pop the stack and replace the top with N ^ T</td>
|
| 513 |
|
|
</tr>
|
| 514 |
|
|
<th align="left"><a href="#nip">nip</a></th>
|
| 515 |
|
|
<td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td>
|
| 516 |
|
|
<td align="left">pop the next-to-top from the data stack</td>
|
| 517 |
|
|
</tr>
|
| 518 |
|
|
<th align="left"><a href="#drop">drop</a></th>
|
| 519 |
|
|
<td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td>
|
| 520 |
|
|
<td align="left">drop the top value from the stack<tt></td>
|
| 521 |
|
|
</tr>
|
| 522 |
|
|
<th align="left"><a href="#1+">1+</a></th>
|
| 523 |
|
|
<td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td>
|
| 524 |
|
|
<td align="left">Add 1 to T</td>
|
| 525 |
|
|
</tr>
|
| 526 |
|
|
<th align="left"><a href="#1-">1-</a></th>
|
| 527 |
|
|
<td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td>
|
| 528 |
|
|
<td align="left">Subtract 1 from T</td>
|
| 529 |
|
|
</tr>
|
| 530 |
|
|
<th align="left"><a href="#store">store</a></th>
|
| 531 |
|
|
<td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>b</td><td>b</td>
|
| 532 |
|
|
<td align="left">Store N in the T'th entry in bank "<tt>bb</tt>", drop the top of the data stack</td>
|
| 533 |
|
|
</tr>
|
| 534 |
|
|
<th align="left"><a href="#fetch">fetch</a></th>
|
| 535 |
|
|
<td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>b</td><td>b</td>
|
| 536 |
|
|
<td align="left">Exchange the top of the stack with the T'th value from bank "<tt>bb</tt>"</td>
|
| 537 |
|
|
</tr>
|
| 538 |
|
|
<th align="left"><a href="#store+">store+</a></th>
|
| 539 |
|
|
<td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>b</td><td>b</td>
|
| 540 |
|
|
<td align="left">Store N in the T'th entry in bank "<tt>bb</tt>", nip the data stack, and increment T</td>
|
| 541 |
|
|
</tr>
|
| 542 |
|
|
<th align="left"><a href="#store-">store-</a></th>
|
| 543 |
|
|
<td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>b</td><td>b</td>
|
| 544 |
|
|
<td align="left">Store N in the T'th entry in bank "<tt>bb</tt>", nip the data stack, and decrement T</td>
|
| 545 |
|
|
</tr>
|
| 546 |
|
|
<th align="left"><a href="#fetch+">fetch+</a></th>
|
| 547 |
|
|
<td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>b</td><td>b</td>
|
| 548 |
|
|
<td align="left">Push the T'th entry from bank "<tt>bb</tt>" into the data stack as N and increment T</td>
|
| 549 |
|
|
</tr>
|
| 550 |
|
|
<th align="left"><a href="#fetch-">fetch-</a></th>
|
| 551 |
|
|
<td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>b</td><td>b</td>
|
| 552 |
|
|
<td align="left">Push the T'th entry from bank "<tt>bb</tt>" into the data stack as N and decrement T</td>
|
| 553 |
|
|
</tr>
|
| 554 |
|
|
<th align="left"><a href="#jump">jump</a></th>
|
| 555 |
|
|
<td>0</td><td>1</td><td>0</td><td>0</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td>
|
| 556 |
|
|
<td align="left">Jump to the address "<tt>x_xxxx_TTTT_TTTT</tt>"</td>
|
| 557 |
|
|
</tr>
|
| 558 |
|
|
<th align="left"><a href="#jumpc">jumpc</a></th>
|
| 559 |
|
|
<td>0</td><td>1</td><td>0</td><td>1</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td>
|
| 560 |
|
|
<td align="left">Conditionally jump to the address "<tt>x_xxxx_TTTT_TTTT</tt>"</td>
|
| 561 |
|
|
</tr>
|
| 562 |
|
|
<th align="left"><a href="#call">call</a></th>
|
| 563 |
|
|
<td>0</td><td>1</td><td>1</td><td>0</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td>
|
| 564 |
|
|
<td align="left">Call the function at address "<tt>x_xxxx_TTTT_TTTT</tt>"</td>
|
| 565 |
|
|
</tr>
|
| 566 |
|
|
<th align="left"><a href="#callc">callc</a></th>
|
| 567 |
|
|
<td>0</td><td>1</td><td>1</td><td>1</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td>
|
| 568 |
|
|
<td align="left">Conditionally call the function at address "<tt>x_xxxx_TTTT_TTTT</tt>"</td>
|
| 569 |
|
|
</tr>
|
| 570 |
|
|
<th align="left"><a href="#push">push</a></th>
|
| 571 |
|
|
<td>1</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td><td>x</td>
|
| 572 |
|
|
<td align="left">Push the 8-bit value "<tt>xxxx_xxxx</tt>" onto the data stack.</td>
|
| 573 |
|
|
</tr>
|
| 574 |
|
|
</table>
|
| 575 |
|
|
<h2><a name="&">Instruction: &</a></h2>
|
| 576 |
|
|
<b>Desription:</b> Pop the data stack and replace the top with the bitwise
|
| 577 |
|
|
and of the previous top and next-to-top.<br/><br/>
|
| 578 |
|
|
<b>Operation:</b><br/><br/>
|
| 579 |
|
|
PC ← PC+1<br/>
|
| 580 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 581 |
|
|
T ← T & N<br/>
|
| 582 |
|
|
N ← <tt>stack--</tt><br/>
|
| 583 |
|
|
<br/>
|
| 584 |
|
|
<h2><a name="+">Instruction: +</a></h2>
|
| 585 |
|
|
<b>Desription:</b> Pop the data stack and replace the top with the
|
| 586 |
|
|
8 sum of the previous top and next-to-top.<br/><br/>
|
| 587 |
|
|
<b>Operation:</b><br/><br/>
|
| 588 |
|
|
PC ← PC+1<br/>
|
| 589 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 590 |
|
|
T ← N + T<br/>
|
| 591 |
|
|
N ← <tt>stack--</tt><br/>
|
| 592 |
|
|
<br/>
|
| 593 |
|
|
<h2><a name="-">Instruction: -</a></h2>
|
| 594 |
|
|
<b>Desription:</b> Pop the data stack and replace the top with the
|
| 595 |
|
|
8 difference of the previous top and next-to-top.<br/><br/>
|
| 596 |
|
|
<b>Operation:</b><br/><br/>
|
| 597 |
|
|
PC ← PC+1<br/>
|
| 598 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 599 |
|
|
T ← N - T<br/>
|
| 600 |
|
|
N ← <tt>stack--</tt><br/>
|
| 601 |
|
|
<br/>
|
| 602 |
|
|
<h2><a name="-1<>">Instruction: -1<></a></h2>
|
| 603 |
|
|
<b>Desription:</b> Set the top of the stack to all ones if the previous
|
| 604 |
|
|
value was not all ones, otherwise set it to all zeros.<br/><br/>
|
| 605 |
|
|
<b>Operation:</b><br/><br/>
|
| 606 |
|
|
PC ← PC+1<br/>
|
| 607 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 608 |
|
|
T ← 0xFF if T!=0xFF, 0x00 otherwise<br/>
|
| 609 |
|
|
N and <tt>stack</tt> unchanged<br/>
|
| 610 |
|
|
<br/>
|
| 611 |
|
|
<h2><a name="-1=">Instruction: -1=</a></h2>
|
| 612 |
|
|
<b>Desription:</b> Set the top of the stack to all ones if the previous
|
| 613 |
|
|
value was all ones, otherwise set it to all zeros.<br/><br/>
|
| 614 |
|
|
<b>Operation:</b><br/><br/>
|
| 615 |
|
|
PC ← PC+1<br/>
|
| 616 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 617 |
|
|
T ← 0xFF if T=0xFF, 0x00 otherwise<br/>
|
| 618 |
|
|
N and <tt>stack</tt> unchanged<br/>
|
| 619 |
|
|
<br/>
|
| 620 |
|
|
<h2><a name="0<>">Instruction: 0<></a></h2>
|
| 621 |
|
|
<b>Desription:</b> Set the top of the stack to all ones if the previous
|
| 622 |
|
|
value was not all zeros, otherwise set it to all zeros.<br/><br/>
|
| 623 |
|
|
<b>Operation:</b><br/><br/>
|
| 624 |
|
|
PC ← PC+1<br/>
|
| 625 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 626 |
|
|
T ← 0xFF if T!=0x00, 0x00 otherwise<br/>
|
| 627 |
|
|
N and <tt>stack</tt> unchanged<br/>
|
| 628 |
|
|
<br/>
|
| 629 |
|
|
<h2><a name="0=">Instruction: 0=</a></h2>
|
| 630 |
|
|
<b>Desription:</b> Set the top of the stack to all ones if the previous
|
| 631 |
|
|
value was all zeros, otherwise set it to all zeros.<br/><br/>
|
| 632 |
|
|
<b>Operation:</b><br/><br/>
|
| 633 |
|
|
PC ← PC+1<br/>
|
| 634 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 635 |
|
|
T ← 0xFF if T=0x00, 0x00 otherwise<br/>
|
| 636 |
|
|
N and <tt>stack</tt> unchanged<br/>
|
| 637 |
|
|
<br/>
|
| 638 |
|
|
<h2><a name="0>>">Instruction: 0>></a></h2>
|
| 639 |
|
|
<b>Desription:</b> Right shift the top of the stack one bit, replacing the
|
| 640 |
|
|
left-most bit with a zero.<br/><br/>
|
| 641 |
|
|
<b>Operation:</b><br/><br/>
|
| 642 |
|
|
PC ← PC+1<br/>
|
| 643 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 644 |
|
|
T ← { 0, T[7], T[6], ..., T[1] }<br/>
|
| 645 |
|
|
N and <tt>stack</tt> unchanged<br/>
|
| 646 |
|
|
<br/>
|
| 647 |
|
|
<h2><a name="1+">Instruction: 1+</a></h2>
|
| 648 |
|
|
<b>Desription:</b> Add 1 to T.<br/><br/>
|
| 649 |
|
|
<b>Operation:</b><br/><br/>
|
| 650 |
|
|
PC ← PC+1<br/>
|
| 651 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 652 |
|
|
T ← T+1<br/>
|
| 653 |
|
|
N and <tt>stack</tt> unchanged<br/>
|
| 654 |
|
|
<br/>
|
| 655 |
|
|
<h2><a name="1-">Instruction: 1-</a></h2>
|
| 656 |
|
|
<b>Desription:</b> Subtract 1 from T.<br/><br/>
|
| 657 |
|
|
<b>Operation:</b><br/><br/>
|
| 658 |
|
|
PC ← PC+1<br/>
|
| 659 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 660 |
|
|
T ← T-1<br/>
|
| 661 |
|
|
N and <tt>stack</tt> unchanged<br/>
|
| 662 |
|
|
<br/>
|
| 663 |
|
|
<h2><a name="1>>">Instruction: 1>></a></h2>
|
| 664 |
|
|
<b>Desription:</b> Right shift the top of the stack one bit, replacing the
|
| 665 |
|
|
left-most bit with a zero.<br/><br/>
|
| 666 |
|
|
<b>Operation:</b><br/><br/>
|
| 667 |
|
|
PC ← PC+1<br/>
|
| 668 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 669 |
|
|
T ← { 1, T[7], T[6], ..., T[1] }<br/>
|
| 670 |
|
|
N and <tt>stack</tt> unchanged<br/>
|
| 671 |
|
|
<br/>
|
| 672 |
|
|
<h2><a name="<<0">Instruction: <<0</a></h2>
|
| 673 |
|
|
<b>Desription:</b> Left shift the top of the stack one bit, replacing the
|
| 674 |
|
|
right-most bit with a zero.
|
| 675 |
|
|
<b>Operation:</b><br/><br/>
|
| 676 |
|
|
PC ← PC+1<br/>
|
| 677 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 678 |
|
|
T ← { T[6], T[5], ..., T[0], 0 }<br/>
|
| 679 |
|
|
N and <tt>stack</tt> unchanged<br/>
|
| 680 |
|
|
<br/>
|
| 681 |
|
|
<h2><a name="<<1">Instruction: <<1</a></h2>
|
| 682 |
|
|
<b>Desription:</b> Left shift the top of the stack one bit, replacing the
|
| 683 |
|
|
right-most bit with a one.<br/>
|
| 684 |
|
|
<b>Operation:</b><br/><br/>
|
| 685 |
|
|
PC ← PC+1<br/>
|
| 686 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 687 |
|
|
T ← { T[6], T[5], ..., T[0], 1 }<br/>
|
| 688 |
|
|
N and <tt>stack</tt> unchanged<br/>
|
| 689 |
|
|
<br/>
|
| 690 |
|
|
<h2><a name="<<msb">Instruction: <<msb</a></h2>
|
| 691 |
|
|
<b>Desription:</b> Left shift the top of the stack one bit, leaving the
|
| 692 |
|
|
right-most bit unchanged.<br/><br/>
|
| 693 |
|
|
<b>Operation:</b><br/><br/>
|
| 694 |
|
|
PC ← PC+1<br/>
|
| 695 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 696 |
|
|
T ← { T[6], T[5], ..., T[0], T[7] }<br/>
|
| 697 |
|
|
N and <tt>stack</tt> unchanged<br/>
|
| 698 |
|
|
<br/>
|
| 699 |
|
|
<h2><a name=">r">Instruction: >r</a></h2>
|
| 700 |
|
|
<b>Desription:</b> Pop the data stack and push its previous value onto the
|
| 701 |
|
|
return stack.<br/><br/>
|
| 702 |
|
|
<b>Operation:</b><br/><br/>
|
| 703 |
|
|
PC ← PC+1<br/>
|
| 704 |
|
|
R ← T<br/>
|
| 705 |
|
|
<tt>++return</tt> ← R<br/>
|
| 706 |
|
|
T ← N<br/>
|
| 707 |
|
|
N ← <tt>stack--</tt><br/>
|
| 708 |
|
|
<br/>
|
| 709 |
|
|
<h2><a name="^">Instruction: ^</a></h2>
|
| 710 |
|
|
<b>Desription:</b> Pop the data stack and replace the top with the bitwise
|
| 711 |
|
|
exclusive or of the previous top and next-to-top.<br/><br/>
|
| 712 |
|
|
<b>Operation:</b><br/><br/>
|
| 713 |
|
|
PC ← PC+1<br/>
|
| 714 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 715 |
|
|
T ← T ^ N<br/>
|
| 716 |
|
|
N ← <tt>stack--</tt><br/>
|
| 717 |
|
|
<br/>
|
| 718 |
|
|
<h2><a name="call">Instruction: call</a></h2>
|
| 719 |
|
|
<b>Desription:</b> Call the function at the address constructed from the
|
| 720 |
|
|
opcode and <tt>T</tt>. Discard <tt>T</tt> and push the PC onto the
|
| 721 |
|
|
return stack.<br/><br/>
|
| 722 |
|
|
<b>Operation:</b><br/><br/>
|
| 723 |
|
|
PC ← { O[4], ..., O[0], T[7], T[6], ..., T[0] }<br/>
|
| 724 |
|
|
R ← PC+1<br/>
|
| 725 |
|
|
<tt>++return</tt> ← R<br/>
|
| 726 |
|
|
T ← N<br/>
|
| 727 |
|
|
N ← <tt>stack--</tt><br/>
|
| 728 |
|
|
<br/>
|
| 729 |
|
|
<b>Special:</b><br/><br/>
|
| 730 |
|
|
Interrupts are disabled during the clock cycle immediately following a
|
| 731 |
|
|
call instruction.<br/><br/>
|
| 732 |
|
|
The assembler normally places a "<tt>nop</tt>" instruction immediately
|
| 733 |
|
|
after the "<tt>call</tt>" instruction.<br/><br/>
|
| 734 |
|
|
<h2><a name="callc">Instruction: callc</a></h2>
|
| 735 |
|
|
<b>Desription:</b> Conditionally call the function at the address
|
| 736 |
|
|
constructed from the opcode and <tt>T</tt>. Discard <tt>T</tt> and
|
| 737 |
|
|
conditionally push the next PC onto the return stack.<br/><br/>
|
| 738 |
|
|
<b>Operation:</b><br/><br/>
|
| 739 |
|
|
if N != 0 then<br/>
|
| 740 |
|
|
PC ← { O[4], ..., O[0], T[7], T[6], ..., T[0] }<br/>
|
| 741 |
|
|
R ← PC<br/>
|
| 742 |
|
|
<tt>++return</tt> ← R<br/>
|
| 743 |
|
|
else<br/>
|
| 744 |
|
|
PC ← PC+1<br/>
|
| 745 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 746 |
|
|
endif<br/>
|
| 747 |
|
|
T ← N<br/>
|
| 748 |
|
|
N ← <tt>stack--</tt><br/>
|
| 749 |
|
|
<br/>
|
| 750 |
|
|
<b>Special:</b><br/><br/>
|
| 751 |
|
|
Interrupts are disabled during the clock cycle immediately following a
|
| 752 |
|
|
callc instruction.<br/><br/>
|
| 753 |
|
|
The assembler normally places a "<tt>drop</tt>" instruction immediately
|
| 754 |
|
|
after the "<tt>callc</tt>" instruction.<br/><br/>
|
| 755 |
|
|
<h2><a name="dis">Instruction: dis</a></h2>
|
| 756 |
|
|
<b>Desription:</b> Disable interrupts.<br/><br/>
|
| 757 |
|
|
<b>Operation:</b><br/><br/>
|
| 758 |
|
|
PC ← PC+1<br/>
|
| 759 |
|
|
R, <tt>return</tt>, T, N, and <tt>stack</tt> unchanged</br>
|
| 760 |
|
|
<br/>
|
| 761 |
|
|
<h2><a name="drop">Instruction: drop</a></h2>
|
| 762 |
|
|
<b>Desription:</b> Pop the data stack, discarding the value that had been
|
| 763 |
|
|
on the top.<br/><br/>
|
| 764 |
|
|
<b>Operation:</b><br/><br/>
|
| 765 |
|
|
PC ← PC+1<br/>
|
| 766 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 767 |
|
|
T ← N<br/>
|
| 768 |
|
|
N ← <tt>stack--</tt><br/>
|
| 769 |
|
|
<br/>
|
| 770 |
|
|
<h2><a name="dup">Instruction: dup</a></h2>
|
| 771 |
|
|
<b>Desription:</b> Push the top of the data stack onto the data
|
| 772 |
|
|
stack.<br/><br/>
|
| 773 |
|
|
<b>Operation:</b><br/><br/>
|
| 774 |
|
|
PC ← PC+1<br/>
|
| 775 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 776 |
|
|
T ← T<br/>
|
| 777 |
|
|
N ← T<br/>
|
| 778 |
|
|
<tt>++stack</tt> ← N<br/>
|
| 779 |
|
|
<br/>
|
| 780 |
|
|
<h2><a name="ena">Instruction: ena</a></h2>
|
| 781 |
|
|
<b>Desription:</b> Enable interrupts.<br/><br/>
|
| 782 |
|
|
<b>Operation:</b><br/><br/>
|
| 783 |
|
|
PC ← PC+1<br/>
|
| 784 |
|
|
R, <tt>return</tt>, T, N, and <tt>stack</tt> unchanged</br>
|
| 785 |
|
|
<br/>
|
| 786 |
|
|
<h2><a name="fetch">Instruction: fetch</a></h2>
|
| 787 |
|
|
<b>Desription:</b> Replace the top of the data stack with an 8 bit
|
| 788 |
|
|
value from memory. The memory bank is specified by the two
|
| 789 |
|
|
least-significant bits of the opcode. The index within the memory bank is
|
| 790 |
|
|
specified by the previous value of the top of the stack.<br/><br/>
|
| 791 |
|
|
<b>Operation:</b><br/><br/>
|
| 792 |
|
|
PC ← PC+1<br/>
|
| 793 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 794 |
|
|
T ← bb[T] where "bb" is the bank<br/>
|
| 795 |
|
|
N and <tt>stack</tt> unchanged<br/>
|
| 796 |
|
|
<b>Special:</b>
|
| 797 |
|
|
See <a href="#memory">memory</a> for instructions on using the fetch and
|
| 798 |
|
|
vectorized fetch macros.<br/>
|
| 799 |
|
|
<br/>
|
| 800 |
|
|
<h2><a name="fetch+">Instruction: fetch+</a></h2>
|
| 801 |
|
|
<b>Desription:</b> Push the T'th entry from bank "<tt>bb</tt>" onto the
|
| 802 |
|
|
data stack as N and increment the top of the data stack.<br/><br/>
|
| 803 |
|
|
<b>Operation:</b><br/><br/>
|
| 804 |
|
|
PC ← PC+1<br/>
|
| 805 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 806 |
|
|
T ← T+1<br/>
|
| 807 |
|
|
N ← bb[T] where "bb" is the bank<br/>
|
| 808 |
|
|
<tt>++stack</tt><br/>
|
| 809 |
|
|
<b>Special:</b>
|
| 810 |
|
|
See <a href="#memory">memory</a> for instructions on using the fetch and
|
| 811 |
|
|
vectorized fetch macros.<br/>
|
| 812 |
|
|
<br/>
|
| 813 |
|
|
<h2><a name="fetch-">Instruction: fetch-</a></h2>
|
| 814 |
|
|
<b>Desription:</b> Push the T'th entry from bank "<tt>bb</tt>" onto the
|
| 815 |
|
|
data stack as N and decrement the top of the data stack.<br/><br/>
|
| 816 |
|
|
<b>Operation:</b><br/><br/>
|
| 817 |
|
|
PC ← PC+1<br/>
|
| 818 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 819 |
|
|
T ← T-1<br/>
|
| 820 |
|
|
N ← bb[T] where "bb" is the bank<br/>
|
| 821 |
|
|
<tt>++stack</tt><br/>
|
| 822 |
|
|
<b>Special:</b>
|
| 823 |
|
|
See <a href="#memory">memory</a> for instructions on using the fetch and
|
| 824 |
|
|
vectorized fetch macros.<br/>
|
| 825 |
|
|
<br/>
|
| 826 |
|
|
<h2><a name="inport">Instruction: inport</a></h2>
|
| 827 |
|
|
<b>Desription:</b> Replace the top of the data stack with the 8 value
|
| 828 |
|
|
from the port specified by the previous value of the top of the data
|
| 829 |
|
|
stack.<br/><br/>
|
| 830 |
|
|
<b>Operation:</b><br/><br/>
|
| 831 |
|
|
PC ← PC+1<br/>
|
| 832 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 833 |
|
|
T ← <tt>input_port</tt>[T]<br/>
|
| 834 |
|
|
N and <tt>stack</tt> unchanged<br/>
|
| 835 |
|
|
<br/>
|
| 836 |
|
|
<b>Special:</b><br/><br/>
|
| 837 |
|
|
The recommended procedure to read from an inport port is to use the
|
| 838 |
|
|
"<tt>.inport</tt>" macro.<br/><br/>
|
| 839 |
|
|
<h2><a name="jump">Instruction: jump</a></h2>
|
| 840 |
|
|
<b>Desription:</b> Jump to the address constructed from the opcode and
|
| 841 |
|
|
<tt>T</tt>. Discard <tt>T</tt>.<br/><br/>
|
| 842 |
|
|
<b>Operation:</b><br/><br/>
|
| 843 |
|
|
PC ← { O[4], ..., O[0], T[7], T[6], ..., T[0] }<br/>
|
| 844 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 845 |
|
|
T ← N<br/>
|
| 846 |
|
|
N ← <tt>stack--</tt><br/>
|
| 847 |
|
|
<br/>
|
| 848 |
|
|
<b>Special:</b><br/><br/>
|
| 849 |
|
|
Interrupts are disabled during the clock cycle immediately following a
|
| 850 |
|
|
jump instruction.<br/><br/>
|
| 851 |
|
|
The assembler normally places a "<tt>nop</tt>" instruction immediately
|
| 852 |
|
|
after the "<tt>jump</tt>" instruction.<br/><br/>
|
| 853 |
|
|
<h2><a name="jumpc">Instruction: jumpc</a></h2>
|
| 854 |
|
|
<b>Desription:</b> Jump to the address constructed from the opcode and
|
| 855 |
|
|
<tt>T</tt> if <tt>N</tt> is non-zero. Discard <tt>S</tt>
|
| 856 |
|
|
and <tt>N</tt>.<br/><br/>
|
| 857 |
|
|
<b>Operation:</b><br/><br/>
|
| 858 |
|
|
if N != 0 then<br/>
|
| 859 |
|
|
PC ← { O[4], ..., O[0], T[7], T[6], ..., T[0] }<br/>
|
| 860 |
|
|
else<br/>
|
| 861 |
|
|
PC ← PC+1<br/>
|
| 862 |
|
|
end if<br/>
|
| 863 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 864 |
|
|
T ← N<br/>
|
| 865 |
|
|
N ← <tt>stack--</tt><br/>
|
| 866 |
|
|
<br/>
|
| 867 |
|
|
<b>Special:</b><br/><br/>
|
| 868 |
|
|
Interrupts are disabled during the clock cycle immediately following a
|
| 869 |
|
|
jumpc instruction.<br/><br/>
|
| 870 |
|
|
The assembler normally places a "<tt>drop</tt>" instruction immediately
|
| 871 |
|
|
after the "<tt>jump</tt>" instruction so that the conditional is dropped
|
| 872 |
|
|
from the data stack.<br/><br/>
|
| 873 |
|
|
<h2><a name="lsb>>">Instruction: lsb>></a></h2>
|
| 874 |
|
|
<b>Desription:</b> Right shift the top of the stack one bit, replacing the
|
| 875 |
|
|
left-most bit with the previous value of the right-most bit.<br/><br/>
|
| 876 |
|
|
<b>Operation:</b><br/><br/>
|
| 877 |
|
|
PC ← PC+1<br/>
|
| 878 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 879 |
|
|
T ← { T[0], T[7], T[6], ..., T[1] }<br/>
|
| 880 |
|
|
N and <tt>stack</tt> unchanged<br/>
|
| 881 |
|
|
<br/>
|
| 882 |
|
|
<h2><a name="msb>>">Instruction: msb>></a></h2>
|
| 883 |
|
|
<b>Desription:</b> Right shift the top of the stack one bit, preserving the
|
| 884 |
|
|
value of the left-most bit.<br/><br/>
|
| 885 |
|
|
<b>Operation:</b><br/><br/>
|
| 886 |
|
|
PC ← PC+1<br/>
|
| 887 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 888 |
|
|
T ← { T[7], T[7], T[6], ..., T[1] }<br/>
|
| 889 |
|
|
N and <tt>stack</tt> unchanged<br/>
|
| 890 |
|
|
<br/>
|
| 891 |
|
|
<h2><a name="nip">Instruction: nip</a></h2>
|
| 892 |
|
|
<b>Desription:</b> Discard the next-to-top value on the data
|
| 893 |
|
|
stack.<br/><br/>
|
| 894 |
|
|
<b>Operation:</b><br/><br/>
|
| 895 |
|
|
PC ← PC+1<br/>
|
| 896 |
|
|
R and <return</tt> unchanged<br/>
|
| 897 |
|
|
T ← T<br/>
|
| 898 |
|
|
N ← <tt>stack--</tt><br/>
|
| 899 |
|
|
<br/>
|
| 900 |
|
|
<h2><a name="nop">Instruction: nop</a></h2>
|
| 901 |
|
|
<b>Desription:</b> No operation.<br/><br/>
|
| 902 |
|
|
<b>Operation:</b><br/><br/>
|
| 903 |
|
|
PC &leftarrow PC + 1<br/>
|
| 904 |
|
|
R, <tt>return</tt>, T, N, and <tt>stack</tt> unchanged<br/>
|
| 905 |
|
|
<br/>
|
| 906 |
|
|
<h2><a name="or">Instruction: or</a></h2>
|
| 907 |
|
|
<b>Desription:</b> Pop the data stack and replace the top with the bitwise
|
| 908 |
|
|
or of the previous top and next-to-top.<br/><br/>
|
| 909 |
|
|
<b>Operation:</b><br/><br/>
|
| 910 |
|
|
PC ← PC+1<br/>
|
| 911 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 912 |
|
|
T ← T or N<br/>
|
| 913 |
|
|
N ← <tt>stack--</tt><br/>
|
| 914 |
|
|
<br/>
|
| 915 |
|
|
<h2><a name="outport">Instruction: outport</a></h2>
|
| 916 |
|
|
<b>Desription:</b> Pop the data stack and write the previous next-to-top to
|
| 917 |
|
|
the port specified by the previous top.<br/>
|
| 918 |
|
|
<b>Operation:</b><br/><br/>
|
| 919 |
|
|
PC ← PC+1<br/>
|
| 920 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 921 |
|
|
T ← N<br/>
|
| 922 |
|
|
N ← <tt>stack--</tt><br/>
|
| 923 |
|
|
<tt>outport</tt>[T] ← N<br/>
|
| 924 |
|
|
<br/>
|
| 925 |
|
|
<b>Special:</b><br/><br/>
|
| 926 |
|
|
This instruction must be following by a "<tt>drop</tt>" in order to
|
| 927 |
|
|
discard the value from the data stack that had been written to the data
|
| 928 |
|
|
port. The recommended procedure to write to an output port is to use the
|
| 929 |
|
|
"<tt>.outport</tt>" macro.<br/><br/>
|
| 930 |
|
|
<h2><a name="over">Instruction: over</a></h2>
|
| 931 |
|
|
<b>Desription:</b> Push the next-to-top of the data stack onto the data
|
| 932 |
|
|
stack.<br/><br/>
|
| 933 |
|
|
<b>Operation:</b><br/><br/>
|
| 934 |
|
|
PC ← PC+1<br/>
|
| 935 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 936 |
|
|
T ← N<br/>
|
| 937 |
|
|
N ← T<br/>
|
| 938 |
|
|
<tt>++stack</tt> ← N<br/>
|
| 939 |
|
|
<br/>
|
| 940 |
|
|
<h2><a name="push">Instruction: push</a></h2>
|
| 941 |
|
|
<b>Description:</b> Push the specified 8-bit value onto the 8-bit
|
| 942 |
|
|
stack.<br/><br/>
|
| 943 |
|
|
<b>Operation:</b><br/><br/>
|
| 944 |
|
|
PC ← PC+1<br/>
|
| 945 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 946 |
|
|
T ← <tt>opcode</tt>[7:0]<br/>
|
| 947 |
|
|
N ← T<br/>
|
| 948 |
|
|
<tt>++stack</tt> ← N<br/>
|
| 949 |
|
|
<br/>
|
| 950 |
|
|
<h2><a name="r>">Instruction: r></a></h2>
|
| 951 |
|
|
<b>Desription:</b> Pop the return stack and push its previous value onto
|
| 952 |
|
|
the data stack.<br/><br/>
|
| 953 |
|
|
<b>Operation:</b><br/><br/>
|
| 954 |
|
|
PC ← PC+1<br/>
|
| 955 |
|
|
R ← <tt>return--</tt><br/>
|
| 956 |
|
|
T ← R<br/>
|
| 957 |
|
|
N ← T<br/>
|
| 958 |
|
|
<tt>++stack</tt> ← N<br/>
|
| 959 |
|
|
<br/>
|
| 960 |
|
|
<h2><a name="r@">Instruction: r@</a></h2>
|
| 961 |
|
|
<b>Desription:</b> Push the top of the return stack onto the data
|
| 962 |
|
|
stack.<br/><br/>
|
| 963 |
|
|
<b>Operation:</b><br/><br/>
|
| 964 |
|
|
PC ← PC+1<br/>
|
| 965 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 966 |
|
|
T ← R<br/>
|
| 967 |
|
|
N ← T<br/>
|
| 968 |
|
|
<tt>++stack</tt> ← N<br/>
|
| 969 |
|
|
<h2><a name="return">Instruction: return</a></h2>
|
| 970 |
|
|
<b>Description:</b> Popd the top of the return stack into the PC.<br/><br/>
|
| 971 |
|
|
<b>Operation:</b><br/><br/>
|
| 972 |
|
|
PC ← R<br/>
|
| 973 |
|
|
R ← <tt>return--</tt><br/>
|
| 974 |
|
|
T, N, and <tt>stack</tt> unchanged<br/>
|
| 975 |
|
|
<br/>
|
| 976 |
|
|
<b>Special:</b>
|
| 977 |
|
|
This instruction must be followed by a "<tt>nop</tt>"
|
| 978 |
|
|
instruction.<br/><br/>
|
| 979 |
|
|
<h2><a name="store">Instruction: store</a></h2>
|
| 980 |
|
|
<b>Desription:</b> Drop the top of the data stack and store the previous
|
| 981 |
|
|
next-to-top of the data stack at the memory location specified by the top
|
| 982 |
|
|
of the data stack. The memory bank is specified by the two least
|
| 983 |
|
|
significant bits of the opcode.<br/><br/>
|
| 984 |
|
|
<b>Operation:</b><br/><br/>
|
| 985 |
|
|
PC ← PC+1<br/>
|
| 986 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 987 |
|
|
T ← N<br/>
|
| 988 |
|
|
N ← <tt>stack--</tt><br/>
|
| 989 |
|
|
bb[T] ← N where "<tt>bb</tt>" is the bank<br/>
|
| 990 |
|
|
<br/>
|
| 991 |
|
|
<b>Special:</b>
|
| 992 |
|
|
See <a href="#memory">memory</a> for instructions on using the store and
|
| 993 |
|
|
vectorized store macros.<br/>
|
| 994 |
|
|
<br/>
|
| 995 |
|
|
<h2><a name="store+">Instruction: store+</a></h2>
|
| 996 |
|
|
<b>Desription:</b> Nip the data stack and store the previous next-to-top of
|
| 997 |
|
|
the data stack at the memory location specified by the top of the data
|
| 998 |
|
|
stack. Increment the top of the data stack The memory bank is specified
|
| 999 |
|
|
by the two least significant bits of the opcode.<br/><br/>
|
| 1000 |
|
|
<b>Operation:</b><br/><br/>
|
| 1001 |
|
|
PC ← PC+1<br/>
|
| 1002 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 1003 |
|
|
T ← T+1<br/>
|
| 1004 |
|
|
N ← <tt>stack--</tt><br/>
|
| 1005 |
|
|
bb[T] ← N where "<tt>bb</tt>" is the bank<br/>
|
| 1006 |
|
|
<br/>
|
| 1007 |
|
|
<b>Special:</b>
|
| 1008 |
|
|
See <a href="#memory">memory</a> for instructions on using the store and
|
| 1009 |
|
|
vectorized store macros.<br/>
|
| 1010 |
|
|
<br/>
|
| 1011 |
|
|
<h2><a name="store-">Instruction: store-</a></h2>
|
| 1012 |
|
|
<b>Desription:</b> Nip the data stack and store the previous next-to-top of
|
| 1013 |
|
|
the data stack at the memory location specified by the top of the data
|
| 1014 |
|
|
stack. Decrement the top of the data stack The memory bank is specified
|
| 1015 |
|
|
by the two least significant bits of the opcode.<br/><br/>
|
| 1016 |
|
|
<b>Operation:</b><br/><br/>
|
| 1017 |
|
|
PC ← PC+1<br/>
|
| 1018 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 1019 |
|
|
T ← T-1<br/>
|
| 1020 |
|
|
N ← <tt>stack--</tt><br/>
|
| 1021 |
|
|
bb[T] ← N where "<tt>bb</tt>" is the bank<br/>
|
| 1022 |
|
|
<br/>
|
| 1023 |
|
|
<b>Special:</b>
|
| 1024 |
|
|
See <a href="#memory">memory</a> for instructions on using the store and
|
| 1025 |
|
|
vectorized store macros.<br/>
|
| 1026 |
|
|
<br/>
|
| 1027 |
|
|
<h2><a name="swap">Instruction: swap</a></h2>
|
| 1028 |
|
|
<b>Desription:</b> Swap the top two values on the data stack.<br/><br/>
|
| 1029 |
|
|
<b>Operation:</b><br/><br/>
|
| 1030 |
|
|
PC ← PC+1<br/>
|
| 1031 |
|
|
R and <tt>return</tt> unchanged<br/>
|
| 1032 |
|
|
T ← N<br/>
|
| 1033 |
|
|
N ← T<br/>
|
| 1034 |
|
|
<tt>stack</tt> unchanged<br/>
|
| 1035 |
|
|
<br/>
|
| 1036 |
|
|
<h1>Assembler</h1>
|
| 1037 |
|
|
This section describes the contents of an assembly language file and the
|
| 1038 |
|
|
instruction format.<br/><br/>
|
| 1039 |
|
|
The following is a simple, 10 instruction sequence, demonstrating a
|
| 1040 |
|
|
loop:<br/><br/>
|
| 1041 |
|
|
<tt> ; consume 256*6+3 clock cycles</tt><br/>
|
| 1042 |
|
|
<tt> 0 :l00 1 - dup .jumpc(l00) drop .return</tt><br/><br/>
|
| 1043 |
|
|
This looks a lot like Forth code in that the operations are single words and
|
| 1044 |
|
|
are strung together on a single line. Unlike traditional assembly
|
| 1045 |
|
|
languages, there are no source and destination registers, so most of the
|
| 1046 |
|
|
operations for this stack-based processor simply manipulate the stack. This
|
| 1047 |
|
|
can make it easier to see the body of the assembly code since an instruction
|
| 1048 |
|
|
sequence can occupy a single line of the file instead of tens of lines of
|
| 1049 |
|
|
vertical space. The exceptions to the single-operand format are labels,
|
| 1050 |
|
|
such as the "<tt>:l00</tt>" which are declared with a single "<tt>:</tt>"
|
| 1051 |
|
|
immediately followed by the name of the label with no intervening spaces;
|
| 1052 |
|
|
jump instructions such as the 3 instruction,
|
| 1053 |
|
|
"<tt>push jumpc drop</tt>", sequence created by the
|
| 1054 |
|
|
"<tt>.jumpc</tt>" macro; and the 2 operand, "<tt>return nop</tt>",
|
| 1055 |
|
|
sequence created by the "<tt>.return</tt>" macro. The "<tt>.jump</tt>",
|
| 1056 |
|
|
"<tt>.jumpc</tt>", "<tt>.call</tt>", and "<tt>.callc</tt>", macros are
|
| 1057 |
|
|
pre-defined in the assembler and ensure that the correct sequence of
|
| 1058 |
|
|
operands is generated for the jump, conditional jump, function call, and
|
| 1059 |
|
|
conditional function call instructions. Similarly, the "<tt>.return</tt>"
|
| 1060 |
|
|
macro is pre-defined in the assember and ensures that the correct sequence
|
| 1061 |
|
|
of operations is done for returning from a called function.<br/><br/>
|
| 1062 |
|
|
Memory does not have to be declared for the processor. For example, the LED
|
| 1063 |
|
|
flashing examples required no variable or constant storage, and therefore do
|
| 1064 |
|
|
not declare or consume resources required for memory. Variable declarations
|
| 1065 |
|
|
are done within pages declared using the "<tt>.memory</tt>" and
|
| 1066 |
|
|
"<tt>.variable</tt>" macros as follows:<br/><br/>
|
| 1067 |
|
|
<tt> .memory RAM myRAM</tt><br/>
|
| 1068 |
|
|
<tt> .variable save_count</tt><br/>
|
| 1069 |
|
|
<tt> .variable old_count 0x0a</tt><br/>
|
| 1070 |
|
|
<tt> .variable out_string .length 16</tt><br/><br/>
|
| 1071 |
|
|
Here, the "<tt>.memory RAM</tt>" macro declares the start of a page
|
| 1072 |
|
|
of RAM. The RAM will be allocated as prescribed in the processor
|
| 1073 |
|
|
description file. Here, the variable "<tt>save_count</tt>" will be at
|
| 1074 |
|
|
memory address "<tt>0x00</tt>" and will occupy a single, uninitialized slot
|
| 1075 |
|
|
of memory. The variable "<tt>old_count</tt>" will also occupy a single slot
|
| 1076 |
|
|
of memory at address "<tt>0x01</tt>" and will be initialized to the hex
|
| 1077 |
|
|
value "<tt>0x0a</tt>". Note that if the processor is reset that this value
|
| 1078 |
|
|
will not be re-initialized. Finally, the variable "<tt>out_string</tt>"
|
| 1079 |
|
|
will start at address "<tt>0x02</tt>" and will occupy 16 bytes of
|
| 1080 |
|
|
memory.<br/><br/>
|
| 1081 |
|
|
A ROM is declared similarly. For example,<br/><br/>
|
| 1082 |
|
|
<tt> .memory ROM myROM</tt><br/>
|
| 1083 |
|
|
<tt> .variable hex_to_ascii '0' '1' '2' '3' '4' '5' '6' '7' ; first 8 characters</tt><br/>
|
| 1084 |
|
|
<tt> '8' '9' 'A' 'B' 'C' 'D' 'E' 'F' ; second 8 characters</tt><br/><br/>
|
| 1085 |
|
|
declares a page of ROM with the 16 element array hex_to_ascii
|
| 1086 |
|
|
initialized with the values required to convert a 4-bit value to the
|
| 1087 |
|
|
corresponding hex ascii character. This also illustrates how the
|
| 1088 |
|
|
initialization sequence (and length determination) can be continued on
|
| 1089 |
|
|
multiple lines. If "<tt>outbyte</tt>" is a function that outputs a
|
| 1090 |
|
|
single byte to a port, then the hex value of a one-byte value can be output
|
| 1091 |
|
|
using the following sequence:<br/><br/>
|
| 1092 |
|
|
<tt> dup 0>> 0>> 0>> 0>> hex_to_ascii + .fetch(myROM) .call(outbyte)</tt><br/>
|
| 1093 |
|
|
<tt> 0x0F and hex_to_ascii + .fetch(myROM) .call(outbyte)</tt><br/><br/>
|
| 1094 |
|
|
The first line extracts the most significant nibble of the byte by right
|
| 1095 |
|
|
shifting it 4 times while filling the left with zeros, adding that value to
|
| 1096 |
|
|
the address "<tt>hex_to_ascii</tt>" to get the corresponding ascii
|
| 1097 |
|
|
character, fetching that value from the ROM named "<tt>myROM</tt>", and then
|
| 1098 |
|
|
calling the function that consumes that value on the top of the stack while
|
| 1099 |
|
|
sending it to the output port (this takes 11 instructions). The second line
|
| 1100 |
|
|
extracts the least significant nibble using an "<tt>and</tt>" instructions
|
| 1101 |
|
|
and then proceeds similarly (this takes 8 instructions). The
|
| 1102 |
|
|
"<tt>.fetch</tt>" macro generates the "<tt>fetch</tt>" instruction using the
|
| 1103 |
|
|
3 bit value of "<tt>myROM</tt>" as part of the memory address
|
| 1104 |
|
|
generation.<br/><br/>
|
| 1105 |
|
|
The "<tt>.store</tt>" macro is similar to the "<tt>.fetch</tt>" macro except
|
| 1106 |
|
|
that the assembler will generate an error message if a "<tt>store</tt>"
|
| 1107 |
|
|
operation is attempted to a ROM page.<br/><br/>
|
| 1108 |
|
|
Two additional variants of the "<tt>.fetch</tt>" and "<tt>.store</tt>" macros
|
| 1109 |
|
|
are provided. The first, "<tt>.fetch(save_count)</tt>" will generate the
|
| 1110 |
|
|
2 instruction sequence consisting of (1) the instruction to push
|
| 1111 |
|
|
the 8 bit address of "<tt>save_count</tt>" onto the stack and
|
| 1112 |
|
|
(2) the "<tt>fetch</tt>" instruction with the 3 bit page number
|
| 1113 |
|
|
associated with "<tt>save_count</tt>". This helps ensure the correct page
|
| 1114 |
|
|
is used when accessing "<tt>save_count</tt>". The instruction
|
| 1115 |
|
|
"<tt>store(save_count)</tt>" is similar. The second variant of these is for
|
| 1116 |
|
|
indexed fetches and stores. For example, the preceding example to convert
|
| 1117 |
|
|
the single-byte value to hex could be written as<br/><br/>
|
| 1118 |
|
|
<tt> dup 0>> 0>> 0>> 0>> .fetchindexed(hex_to_ascii) .call(outbyte)</tt><br/>
|
| 1119 |
|
|
<tt> 0x0F and .fetchindexed(hex_to_ascii) .call(outbyte)</tt><br/><br/>
|
| 1120 |
|
|
Here, the macro "<tt>.fetchindexed</tt>" consumes the top of the data stack
|
| 1121 |
|
|
as an index into the array variable "<tt>hex_to_ascii</tt>" and pushes the
|
| 1122 |
|
|
indexed value onto the top of the data stack.<br/><br/>
|
| 1123 |
|
|
The "<tt>store</tt>" instruction must be followed by a drop instruction since
|
| 1124 |
|
|
it consumes the top two values in the data stack. The "<tt>.store</tt>" and
|
| 1125 |
|
|
"<tt>.storeindexed</tt>" macros generate this drop function automatically.
|
| 1126 |
|
|
Thus, "<tt>.store(myRAM)</tt>" generates the 2 instruction sequence
|
| 1127 |
|
|
"<tt>store drop</tt>", "<tt>.store(save_count)</tt>" generates the
|
| 1128 |
|
|
3 instruction sequence "<tt>save_count store drop</tt>", and
|
| 1129 |
|
|
"<tt>.storeindexed(out_string)</tt>" generates the 4 instruction
|
| 1130 |
|
|
sequence "<tt>out_string + store drop</tt>", all with the
|
| 1131 |
|
|
proviso that the "<tt>store</tt>" instructions include the 3 bit
|
| 1132 |
|
|
address "<tt>myRAM</tt>".<br/><br/>
|
| 1133 |
|
|
<h2>Program Structure</h2>
|
| 1134 |
|
|
<h2>Directives</h2>
|
| 1135 |
|
|
Alphebetic listing:
|
| 1136 |
|
|
<a href="#.abbr">.abbr</a>,
|
| 1137 |
|
|
<a href="#.constant">.constant</a>,
|
| 1138 |
|
|
<a href="#.function">.function</a>,
|
| 1139 |
|
|
<a href="#.include">.include</a>,
|
| 1140 |
|
|
<a href="#.interrupt">.interrupt</a>,
|
| 1141 |
|
|
<a href="#.main">.main</a>,
|
| 1142 |
|
|
<a href="#.memory">.memory</a>,
|
| 1143 |
|
|
and <a href="#.variable">.variable</a>.<br/><br/>
|
| 1144 |
|
|
<h3><a name=".abbr">.abbr</a></h3>
|
| 1145 |
|
|
TODO
|
| 1146 |
|
|
<h3><a name=".constant">.constant</a></h3>
|
| 1147 |
|
|
TODO
|
| 1148 |
|
|
<h3><a name=".function">.function</a></h3>
|
| 1149 |
|
|
TODO
|
| 1150 |
|
|
<h3><a name=".include">.include</a></h3>
|
| 1151 |
|
|
TODO
|
| 1152 |
|
|
<h3><a name=".interrupt">.interrupt</a></h3>
|
| 1153 |
|
|
TODO
|
| 1154 |
|
|
<h3><a name=".main">.main</a></h3>
|
| 1155 |
|
|
TODO
|
| 1156 |
|
|
<h3><a name=".memory">.memory</a></h3>
|
| 1157 |
|
|
TODO
|
| 1158 |
|
|
<h3><a name=".variable">.variable</a></h3>
|
| 1159 |
|
|
TODO
|
| 1160 |
|
|
<h2>Macros</h2>
|
| 1161 |
|
|
Alphebetic listing:
|
| 1162 |
|
|
<a href="#.call">.call</a>,
|
| 1163 |
|
|
<a href="#.callc">.callc</a>,
|
| 1164 |
|
|
<a href="#.fetch">.fetch</a>,
|
| 1165 |
|
|
<a href="#.fetch+">.fetch+</a>,
|
| 1166 |
|
|
<a href="#.fetch-">.fetch-</a>,
|
| 1167 |
|
|
<a href="#.fetchindexed">.fetchindexed</a>,
|
| 1168 |
|
|
<a href="#.fetchvalue">.fetchvalue</a>,
|
| 1169 |
|
|
<a href="#.fetchvector">.fetchvector</a>,
|
| 1170 |
|
|
<a href="#.inport">.inport</a>,
|
| 1171 |
|
|
<a href="#.jump">.jump</a>,
|
| 1172 |
|
|
<a href="#.jumpc">.jumpc</a>,
|
| 1173 |
|
|
<a href="#.outport">.outport</a>,
|
| 1174 |
|
|
<a href="#.return">.return</a>,
|
| 1175 |
|
|
<a href="#.store">.store</a>,
|
| 1176 |
|
|
<a href="#.store+">.store+</a>,
|
| 1177 |
|
|
<a href="#.store-">.store-</a>,
|
| 1178 |
|
|
<a href="#.storeindexed">.storeindexed</a>,
|
| 1179 |
|
|
<a href="#.storevalue">.storevalue</a>,
|
| 1180 |
|
|
and <a href="#.storevector">.storevector</a>.<br/><br/>
|
| 1181 |
|
|
<h3><a name=".call">.call</a></h3>
|
| 1182 |
|
|
TODO
|
| 1183 |
|
|
<h3><a name=".callc">.callc</a></h3>
|
| 1184 |
|
|
TODO
|
| 1185 |
|
|
<h3><a name=".fetch">.fetch</a></h3>
|
| 1186 |
|
|
TODO
|
| 1187 |
|
|
<h3><a name=".fetch-">.fetch-</a></h3>
|
| 1188 |
|
|
TODO
|
| 1189 |
|
|
<h3><a name=".fetch+">.fetch+</a></h3>
|
| 1190 |
|
|
TODO
|
| 1191 |
|
|
<h3><a name=".fetchindexed">.fetchindexed</a></h3>
|
| 1192 |
|
|
TODO
|
| 1193 |
|
|
<h3><a name=".fetchvalue">.fetchvalue</a></h3>
|
| 1194 |
|
|
TODO
|
| 1195 |
|
|
<h3><a name=".fetchvector">.fetchvector</a></h3>
|
| 1196 |
|
|
TODO
|
| 1197 |
|
|
<h3><a name=".inport">.inport</a></h3>
|
| 1198 |
|
|
TODO
|
| 1199 |
|
|
<h3>.jump</h3>
|
| 1200 |
|
|
<b>Description:</b> Generate the 3 instruction sequence associated with a <tt>jump</tt> instruction.<br/><br/>
|
| 1201 |
|
|
<b>Operation(1):</b> <tt>.jump(label)</tt> generates the following 3 instructions:<br/>
|
| 1202 |
|
|
1 — push the 8 lsb of the label address onto the data stack<br/>
|
| 1203 |
|
|
2 — jump with the 5 msb of the label address encoded in the jump instruction<br/>
|
| 1204 |
|
|
3 — no operation<br/><br/>
|
| 1205 |
|
|
<b>Operation(2):</b> <tt>.jump(label,op)</tt> where "op" is an instruction generates the following 3 instructions:<br/>
|
| 1206 |
|
|
1 — push the 8 lsb of the label address onto the data stack<br/>
|
| 1207 |
|
|
2 — jump with the 5 msb of the label address encoded in the jump instruction<br/>
|
| 1208 |
|
|
3 — op<br/><br/>
|
| 1209 |
|
|
Note that Operation(1) is a special case of Operation(2) with "op" being the <tt>nop</tt> instruction.<br/>
|
| 1210 |
|
|
<h3>.jumpc</h3>
|
| 1211 |
|
|
<b>Description:</b> Generate the 3 instruction sequence associated with a <tt>jumpc</tt> instruction.<br/><br/>
|
| 1212 |
|
|
<b>Operation(1):</b> <tt>.jumpc(label)</tt> generates the following 3 instructions:<br/>
|
| 1213 |
|
|
1 — push the 8 lsb of the label address onto the data stack<br/>
|
| 1214 |
|
|
2 — jump with the 5 msb of the label address encoded in the jump instruction<br/>
|
| 1215 |
|
|
3 — drop<br/><br/>
|
| 1216 |
|
|
<b>Operation(2):</b> <tt>.jumpc(label,op)</tt> where "op" is an instruction generates the following 3 instructions:<br/>
|
| 1217 |
|
|
1 — push the 8 lsb of the label address onto the data stack<br/>
|
| 1218 |
|
|
2 — jump with the 5 msb of the label address encoded in the jumpc instruction<br/>
|
| 1219 |
|
|
3 — op<br/><br/>
|
| 1220 |
|
|
Note that Operation(1) is a special case of Operation(2) with "op" being the <tt>drop</tt> instruction.<br/>
|
| 1221 |
|
|
<h3><a name=".outport">.outport</a></h3>
|
| 1222 |
|
|
TODO
|
| 1223 |
|
|
<h3><a name=".return">.return</a></h3>
|
| 1224 |
|
|
TODO
|
| 1225 |
|
|
<h3><a name=".store">.store</a></h3>
|
| 1226 |
|
|
TODO
|
| 1227 |
|
|
<h3><a name=".store-">.store-</a></h3>
|
| 1228 |
|
|
TODO
|
| 1229 |
|
|
<h3><a name=".store+">.store+</a></h3>
|
| 1230 |
|
|
TODO
|
| 1231 |
|
|
<h3><a name=".storeindexed">.storeindexed</a></h3>
|
| 1232 |
|
|
TODO
|
| 1233 |
|
|
<h3><a name=".storevalue">.storevalue</a></h3>
|
| 1234 |
|
|
TODO
|
| 1235 |
|
|
<h3><a name=".storevector">.storevector</a></h3>
|
| 1236 |
|
|
TODO
|
| 1237 |
|
|
</body>
|
| 1238 |
|
|
</html>
|
