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sinclairrf |
################################################################################
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#
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# Copyright 2013, Sinclair R.F., Inc.
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#
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################################################################################
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import math
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import re;
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from ssbccPeripheral import SSBCCperipheral
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from ssbccUtil import SSBCCException;
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class AXI4_Lite_Master(SSBCCperipheral):
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"""
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AXI-Lite master for 32-bit reads and 8, 16, and 32-bit writes.\n
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256 bytes addressable by a single 8-bit value. The data is stored in little
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endian format (i.e., the LSB of the 32-bit word is stored in the lowest
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numbered address).\n
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Usage:
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PERIPHERAL AXI4_Lite_Master \\
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basePortName=<name> \\
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address=<O_address> \\
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data=<O_data> \\
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write_enable=<O_write_enable> \\
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command_read=<O_command_read> \\
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command_write=<O_command_write> \\
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busy=<I_busy> \\
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error=<I_error> \\
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read=<I_read> \\
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address_width=<N> \\
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synchronous={True|False}
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Where:
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basePortName=<name>
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specifies the name used to construct the multiple AXI4-Lite signals
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address=<O_address>
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specifies the symbol used to set the address used for read and write
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operations from and to the dual-port memory
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Note: If the address is 8 bits or less, a single write to this port will
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set the address. If the address is 9 bits or longer, then multiple
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writes to this address, starting with the MSB of the address, are
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required to set all of the address bits. See the examples for
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illustrations of how this works.
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Note: The 2 lsb of the address are ignored. I.e., all addresses will be
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treated as 32-bit aligned.
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data=<O_data>
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specifies the symbol used to set the 32-bit data for write operations
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Note: Four outputs to this address are required, starting with the MSB of
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the 32-bit value, See the examples for illustrations of how this
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works.
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write_enable=<O_write_enable>
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specifies the symbol used to set the 4 write enable bits
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command_read=<O_command_read>
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specifies the symbol used to start the AXI4-Lite master core to issue a
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read and store the received data
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command_write=<O_command_write>
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specifies the symbol used to start the AXI4-Lite master core to issue a
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write
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busy=<I_busy>
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specifies the symbol used to read the busy/not-busy status of the core
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Note: A non-zero value means the core is busy.
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error=<I_error>
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specified the symbol used to read the error status of the last write or
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read transaction on the core
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Note: A non-zero value means an error was encountered. Errors can be
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reset by resetting the interface or by re-attempting the write or
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read operation.
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read=<I_read>
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specifies the symbol used to read successive bytes of the received 32-bit
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value starting with the LSB
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address_width=<N>
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specifies the width of the 8-bit aligned address\n
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synchronous={True|False}
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indicates whether or not he micro controller clock and the AXI4-Lite bus
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are synchronous
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Example: Xilinx' AXI_DMA core has a 7-bit address range for its register
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address map. The PERIPHERAL configuration statement to interface to this
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core would be:\n
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PERIPHERAL AXI4_Lite_Master \
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basePortName=myAxiDmaDevice \
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address=O_myAxiDmaDevice_address \
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data=O_myAxiDmaDevice_data \
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write_enable=O_myAxiDmaDevice_wen \
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command_read=O_myAxiDmaDevice_cmd_read \
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command_write=O_myAxiDmaDevice_cmd_write \
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busy=I_myAxiDmaDevice_busy \
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error=I_myAxiDmaDevice_error \
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read=I_myAxiDmaDevice_read \
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address_width=7 \
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synchronous=True\n
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To write to the memory master to slave start address, use the
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following, where "start_address" is a 4-byte variable set elsewhere in the
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program:\n
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; Set the 7-bit register address.
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0x18 .outport(O_myAxiDmaDevice_address)
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; Read the 4-byte start address from memory.
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.fetchvector(start_address,4)
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; write the address to the AXI4-Lite master
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${4-1} :loop_data
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swap .outport(O_myAxiDmaDevice_data)
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.jumpc(loop_data,1-) drop
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; Ensure all 4 bytes will be written.
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0x0F .outport(O_myAxiDmaDevice_wen)
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; Issue the write strobe.
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.outstrobe(O_myAxiDmaDevice_cmd_write)
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; Wait for the write operation to finish.
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:loop_write_wait
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.inport(I_myAxiDmaDevice_busy)
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.jumpc(loop_write_wait)\n
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Alternatively, a function could be defined as follows:\n
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; Write the specified 32-bit value to the specified 7-bit address.
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; ( u_LSB u u u_MSB u_addr - )
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.function myAxiDmaDevice_write
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; Write the 7-bit register address.
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.outport(O_myAxiDmaDevice_address)
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; Write the 32-bit value, starting with the MSB.
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${4-1} :loop_data
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swap .outport(O_myAxiDmaDevice_data)
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.jumpc(loop_data,1-) drop
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; Ensure all 4 bytes will be written.
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0x0F .outport(O_myAxiDmaDevice_wen)
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; Issue the write strobe.
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.outstrobe(O_myAxiDmaDevice_cmd_write)
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; Wait for the write operation to finish.
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:loop_write_wait
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.inport(I_myAxiDmaDevice_busy)
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.jumpc(loop_write_wait)
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; That's all
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.return\n
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And the write could then be performed using the following code:\n
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.constant AXI_DMA_MM2S_Start_Address 0x18
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...
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; Write the start address to the AXI DMA.
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.fetchvector(start_address,4)
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.call(myAxiDmaDevice_write,AXI_DMA_MM2S_Start_Address)\n
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Example: Suppose the AXI4-Lite Master peripheral is connected to a memory
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with a 22-bit address width, i.e., a 4 MB address range. The PERIPHERAL
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configuration command would be similar to the above except the string
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"myAxiDmaDevice" would need to be changed to the new hardware peripheral and
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the address width would be set using "address_width=22".\n
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The 22-bit address would be set using 3 bytes. For example, the address
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0x020100 would be set by:\n
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0x00 .outport(O_myAxiMaster_address)
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0x01 .outport(O_myAxiMaster_address)
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0x02 .outport(O_myAxiMaster_address)\n
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The 2 msb of the first, most-significant, address byte will be dropped by
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the shift register receiving the address and the 2 lsb of the last, least
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significant, address byte will be written as zeros to the AXI Lite
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peripheral.\n
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LEGAL NOTICE: ARM has restrictions on what kinds of applications can use
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interfaces based on their AXI protocol. Ensure your application is in
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compliance with their restrictions before using this peripheral for an AXI
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interface.
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"""
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def __init__(self,peripheralFile,config,param_list,loc):
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# Use the externally provided file name for the peripheral
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self.peripheralFile = peripheralFile;
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# Get the parameters.
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allowables = (
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('address', r'O_\w+$', None, ),
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('address_width', r'[1-9]\d*$', int, ),
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('basePortName', r'\w+$', None, ),
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('command_read', r'O_\w+$', None, ),
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('command_write', r'O_\w+$', None, ),
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('data', r'O_\w+$', None, ),
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('read', r'I_\w+$', None, ),
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('busy', r'I_\w+$', None, ),
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('error', r'I_\w+$', None, ),
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('synchronous', r'(True|False)$', bool, ),
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('write_enable', r'O_\w+$', None, ),
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);
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names = [a[0] for a in allowables];
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for param_tuple in param_list:
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param = param_tuple[0];
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if param not in names:
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raise SSBCCException('Unrecognized parameter "%s" at %s' % (param,loc,));
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param_test = allowables[names.index(param)];
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self.AddAttr(config,param,param_tuple[1],param_test[1],loc,param_test[2]);
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# Ensure the required parameters are provided (all parameters are required).
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for paramname in names:
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if not hasattr(self,paramname):
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raise SSBCCException('Required parameter "%s" is missing at %s' % (paramname,loc,));
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# There are no optional parameters.
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# Temporary: Warning message
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if not self.synchronous:
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raise SSBCCException('synchronous=False has not been validated yet');
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# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
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for signal in (
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( 'i_%s_aresetn', 1, 'input', ),
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( 'i_%s_aclk', 1, 'input', ),
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( 'o_%s_awvalid', 1, 'output', ),
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( 'i_%s_awready', 1, 'input', ),
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( 'o_%s_awaddr', self.address_width, 'output', ),
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( 'o_%s_wvalid', 1, 'output', ),
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( 'i_%s_wready', 1, 'input', ),
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( 'o_%s_wdata', 32, 'output', ),
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( 'o_%s_wstrb', 4, 'output', ),
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( 'i_%s_bresp', 2, 'input', ),
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( 'i_%s_bvalid', 1, 'input', ),
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( 'o_%s_bready', 1, 'output', ),
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( 'o_%s_arvalid', 1, 'output', ),
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( 'i_%s_arready', 1, 'input', ),
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( 'o_%s_araddr', self.address_width, 'output', ),
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( 'i_%s_rvalid', 1, 'input', ),
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( 'o_%s_rready', 1, 'output', ),
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( 'i_%s_rdata', 32, 'input', ),
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( 'i_%s_rresp', 2, 'input', ),
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):
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thisName = signal[0] % self.basePortName;
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config.AddIO(thisName,signal[1],signal[2],loc);
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config.AddSignal('s__%s__address' % self.basePortName, self.address_width, loc);
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config.AddSignal('s__%s__rd' % self.basePortName, 1, loc);
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config.AddSignal('s__%s__wr' % self.basePortName, 1, loc);
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config.AddSignal('s__%s__busy' % self.basePortName, 5, loc);
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config.AddSignal('s__%s__error' % self.basePortName, 2, loc);
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config.AddSignal('s__%s__read' % self.basePortName, 32, loc);
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self.ix_address = config.NOutports();
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config.AddOutport((self.address,False,
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# empty list -- disable normal output port signal generation
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),loc);
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self.ix_data = config.NOutports();
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config.AddOutport((self.data,False,
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# empty list -- disable normal output port signal generation
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),loc);
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config.AddOutport((self.write_enable,False,
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('o_%s_wstrb' % self.basePortName, 4, 'data', ),
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),loc);
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config.AddOutport((self.command_read,True,
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('s__%s__rd' % self.basePortName, 1, 'strobe', ),
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),loc);
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config.AddOutport((self.command_write,True,
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('s__%s__wr' % self.basePortName, 1, 'strobe', ),
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),loc);
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config.AddInport((self.busy,
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('s__%s__busy' % self.basePortName, 5, 'data', ),
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),loc);
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config.AddInport((self.error,
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('s__%s__error' % self.basePortName, 2, 'data', ),
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),loc);
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self.ix_read = config.NInports();
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config.AddInport((self.read,
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('s__%s__read' % self.basePortName, 32, 'data', ),
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),loc);
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def GenVerilog(self,fp,config):
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body = self.LoadCore(self.peripheralFile,'.v');
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# avoid i_clk and i_rst
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for subpair in (
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(r'\bgen__', 'gen__@NAME@__', ),
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(r'\bL__', 'L__@NAME@__', ),
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(r'\bs__', 's__@NAME@__', ),
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(r'\bi_a', 'i_@NAME@_a', ),
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(r'\bi_b', 'i_@NAME@_b', ),
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(r'\bi_rd', 'i_@NAME@_rd', ),
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(r'\bi_rr', 'i_@NAME@_rr', ),
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(r'\bi_rv', 'i_@NAME@_rv', ),
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(r'\bi_w', 'i_@NAME@_w', ),
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(r'\bo_', 'o_@NAME@_', ),
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(r'@ADDRESS_WIDTH@', str(self.address_width), ),
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(r'@ISSYNC@', "1'b1" if self.synchronous else "1'b0", ),
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(r'@IX_ADDRESS@', str(self.ix_address), ),
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(r'@IX_DATA@', str(self.ix_data), ),
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(r'@IX_READ@', str(self.ix_read), ),
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(r'@NAME@', self.basePortName, ),
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):
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body = re.sub(subpair[0],subpair[1],body);
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body = self.GenVerilogFinal(config,body);
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fp.write(body);
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