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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [AXI4_Lite_Master.v] - Blame information for rev 7

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1 2 sinclairrf 
//
2 
// PERIPHERAL:  AXI4-Lite Master
3 
//
4 
generate
5 
localparam L__ADDRESS_WIDTH = @ADDRESS_WIDTH@;
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localparam L__ISSYNC = @ISSYNC@;
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localparam L__RESP_OKAY = 2'b00;
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// Shift 8-bit values into the output 32-bit word.
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initial o_wdata = 32'd0;
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always @ (posedge i_clk)
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  if (i_rst)
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    o_wdata <= 32'd0;
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  else if (s_outport && (s_T == 8'd@IX_DATA@))
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    o_wdata <= { o_wdata[0+:24], s_N };
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  else
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    o_wdata <= o_wdata;
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// Shift 8-bit values into the common output address and coerce 2 lsb of output
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// addresses to 0.
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reg [L__ADDRESS_WIDTH-1:0] s__addr = @ADDRESS_WIDTH@'d0;
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if (L__ADDRESS_WIDTH <= 8) begin : gen__short_addr
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  always @ (posedge i_clk)
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    if (i_rst)
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      s__addr <= @ADDRESS_WIDTH@'d0;
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    else if (s_outport && (s_T == 8'd@IX_ADDRESS@))
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      s__addr <= s_N[0+:L__ADDRESS_WIDTH];
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    else
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      s__addr <= s__addr;
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end else begin : gen__long_addr
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  always @ (posedge i_clk)
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    if (i_rst)
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      s__addr <= @ADDRESS_WIDTH@'d0;
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    else if (s_outport && (s_T == 8'd@IX_ADDRESS@))
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      s__addr <= { s__addr[L__ADDRESS_WIDTH-9:0], s_N };
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    else
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      s__addr <= s__addr;
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end
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always @ (*) begin
38 6 sinclairrf 
  o_awaddr = { s__addr[L__ADDRESS_WIDTH-1:2], 2'b00 };
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  o_araddr = { s__addr[L__ADDRESS_WIDTH-1:2], 2'b00 };
40 2 sinclairrf 
end
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// Either use the raw write strobe or synchronize the write strobe.
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wire s__wr_aclk;
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if (L__ISSYNC) begin : gen__sync_wr
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  assign s__wr_aclk = s__wr;
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end else begin : gen__async_wr
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  reg s__wr_toggle = 1'b0;
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  always @ (posedge i_clk)
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    s__wr_toggle <= s__wr ^ s__wr_toggle;
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  reg [3:0] s__wr_s = 4'd0;
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  always @ (i_aclk)
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    s__wr_s <= { s__wr_s[0+:3], s__wr_toggle };
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  reg s__wr_aclk_out = 1'b0;
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  always @ (posedge i_aclk)
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    s__wr_aclk_out <= ^s__wr_s[2+:2];
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  assign s__wr_aclk = s__wr_aclk_out;
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end
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// Write side of the bus.
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initial o_awvalid = 1'b0;
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initial o_wvalid  = 1'b0;
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initial o_bready  = 1'b0;
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reg [2:0] s__pending_wr = 3'h0;
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always @ (posedge i_aclk)
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  if (~i_aresetn) begin
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    o_awvalid <= 1'b0;
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    o_wvalid  <= 1'b0;
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    o_bready  <= 1'b0;
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    s__pending_wr <= 3'h0;
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  end else begin
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    o_awvalid <= o_awvalid;
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    o_wvalid  <= o_wvalid;
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    o_bready  <= o_bready;
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    s__pending_wr <= s__pending_wr;
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    if (s__wr_aclk) begin
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      o_awvalid <= 1'b1;
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      o_wvalid  <= 1'b1;
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      o_bready  <= 1'b0;
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      s__pending_wr <= 3'b111;
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    end else begin
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      if (i_awready) begin
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        o_awvalid <= 1'b0;
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        s__pending_wr[0] <= 1'b0;
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      end
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      if (i_wready) begin
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        o_wvalid <= 1'b0;
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        s__pending_wr[1] <= 1'b0;
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      end
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      if (i_bvalid) begin
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        if (!o_bready)
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          o_bready <= 1'b1;
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        else begin
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          o_bready <= 1'b0;
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          s__pending_wr[2] <= 1'b0;
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        end
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      end
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    end
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  end
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// Either use the raw read strobe or synchronize the read strobe.
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wire s__rd_aclk;
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if (L__ISSYNC) begin : gen__sync_rd
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  assign s__rd_aclk = s__rd;
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end else begin : gen__async_rd
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  reg s__rd_toggle = 1'b0;
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  always @ (posedge i_clk)
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    s__rd_toggle <= s__rd ^ s__rd_toggle;
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  reg [3:0] s__rd_s = 4'd0;
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  always @ (i_aclk)
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    s__rd_s <= { s__rd_s[0+:3], s__rd_toggle };
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  reg s__rd_aclk_out = 1'b0;
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  always @ (posedge i_aclk)
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    s__rd_aclk_out <= ^s__rd_s[2+:2];
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  assign s__rd_aclk = s__rd_aclk_out;
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end
114 
 
115 
// Generate the read address valid signal and record the address acknowledgement
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// pending status.
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reg s__pending_rd_aclk = 1'b0;
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always @ (posedge i_aclk)
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  if (~i_aresetn) begin
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    o_arvalid <= 1'b0;
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    s__pending_rd_aclk <= 1'b0;
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  end else if (s__rd_aclk) begin
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    o_arvalid <= 1'b1;
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    s__pending_rd_aclk <= 1'b1;
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  end else if (i_arready) begin
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    o_arvalid <= 1'b0;
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    s__pending_rd_aclk <= 1'b0;
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  end else begin
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    o_arvalid <= o_arvalid;
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    s__pending_rd_aclk <= s__pending_rd_aclk;
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  end
132 
 
133 
// Generate a strobe from the i_aclk domain to the i_clk domain to latch the
134 
// incoming read data and then generate a strobe in the reverse direction to
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// acknowledge the data.
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wire s__latch_read;
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if (L__ISSYNC) begin : gen__sync_read_ack
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  always @ (posedge i_aclk)
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    if (~i_aresetn)
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      o_rready <= 1'b0;
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    else
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      o_rready <= i_rvalid && ~o_rready;
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  assign s__latch_read = o_rready;
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end else begin : gen__async_read_ack
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  reg s__rvalid_toggle = 1'b0;
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  always @ (i_aclk)
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    if (~i_aresetn)
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      s__rvalid_toggle <= 1'b0;
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    else if (s__rd_aclk)
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      s__rvalid_toggle <= 1'b0;
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    else if (i_rvalid)
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      s__rvalid_toggle <= 1'b1;
153 
    else
154 
      s__rvalid_toggle <= s__rvalid_toggle;
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  reg [3:0] s__rvalid_toggle_s = 4'd0;
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  always @ (posedge i_clk)
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    s__rvalid_toggle_s <= { s__rvalid_toggle_s[0+:2], s__rvalid_toggle };
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  reg s__latch_read_p = 1'b0;
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  always @ (posedge i_clk)
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    if (i_rst)
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      s__latch_read_p <= 1'b0;
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    else
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      s__latch_read_p <= (s__rvalid_toggle_s[2+:2] == 2'b01);
164 
  assign s__latch_read = s__latch_read_p;
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  reg s__latch_toggle = 1'b0;
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  always @ (posedge i_clk)
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    if (i_rst)
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      s__latch_toggle <= 1'b0;
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    else if (s__rd)
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      s__latch_toggle <= 1'b0;
171 
    else if (s__latch_read_p)
172 
      s__latch_toggle <= 1'b1;
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    else
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      s__latch_toggle <= s__latch_toggle;
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  reg [3:0] s__latch_toggle_s = 4'd0;
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  always @ (posedge i_aclk)
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    s__latch_toggle_s <= { s__latch_toggle_s[0+:3], s__latch_toggle };
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  always @ (posedge i_aclk)
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    if (~i_aresetn)
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      o_rready <= 1'b0;
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    else if (s__rd_aclk)
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      o_rready <= 1'b0;
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    else
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      o_rready <= (s__latch_toggle_s[2+:2] == 2'b01);
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end
186 
 
187 
// Track the "pending" status of the data acknowledgement.
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reg s__pending_rd_clk = 1'b0;
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always @ (posedge i_clk)
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  if (i_rst)
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    s__pending_rd_clk <= 1'b0;
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  else if (s__rd)
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    s__pending_rd_clk <= 1'b1;
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  else if (s__latch_read)
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    s__pending_rd_clk <= 1'b0;
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  else
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    s__pending_rd_clk <= s__pending_rd_clk;
198 
 
199 
// Store the received value in a 32-bit word and right shift it when it's read.
200 
always @ (posedge i_clk)
201 
  if (i_rst)
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    s__read <= 32'd0;
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  else if (s__latch_read)
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    s__read <= i_rdata;
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  else if (s_inport && (s_T == 8'd@IX_READ@))
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    s__read <= { 8'd0, s__read[8+:24] };
207 
 
208 
// Composite status (non-zero indicates the bus has not finished the last
209 
// transaction).
210 
always @ (posedge i_clk)
211 
  s__busy <= { s__pending_rd_clk, s__pending_rd_aclk, s__pending_wr };
212 
 
213 
// Monitor the bresp and rresp 2-bit signals for non-OK indication
214 
always @ (posedge i_aclk)
215 
  if (~i_aresetn)
216 
    s__error <= 2'd0;
217 
  else begin
218 
    if (i_bvalid && o_bready) s__error[0] <= (i_bresp != L__RESP_OKAY);
219 
    if (i_rvalid && o_rready) s__error[1] <= (i_rresp != L__RESP_OKAY);
220 
  end
221 
 
222 
endgenerate

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