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################################################################################
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#
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# Copyright 2013-2014, Sinclair R.F., Inc.
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#
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################################################################################
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import math
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import re;
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from ssbccPeripheral import SSBCCperipheral
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from ssbccUtil import SSBCCException;
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class AXI4_Lite_Slave_DualPortRAM(SSBCCperipheral):
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"""
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AXI-Lite slave implemented as a dual-port RAM. The dual-port RAM has at most
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256 bytes addressable by a single 8-bit value. The data is stored in little
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endian format (i.e., the LSB of the 32-bit word is stored in the lowest
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numbered address).\n
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Usage:
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PERIPHERAL AXI4_Lite_Slave_DualPortRAM \\
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basePortName=<name> \\
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address=<O_address> \\
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read=<I_read> \\
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write=<O_write> \\
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[size=<N>] \\
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[ram8|ram32]\n
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Where:
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basePortName=<name>
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specifies the name used to construct the multiple AXI4-Lite signals
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address=<O_address>
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specifies the symbol used to set the address used for read and write
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operations from and to the dual-port memory
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read=<I_read>
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specifies the symbol used to read from the dual-port memory
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write=<O_write>
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specifies the symbol used to write to the dual-port memory
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size=<N>
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optionally specify the size of the dual-port memory.
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Note: N must be either a power of 2 in the range from 16 to 256 inclusive
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or it must be a local param with the same restrictions on its
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value.
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Note: N=256, i.e., the largest memory possible, is the default.
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Note: Using a localparam for the memory size provides a convenient way
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to use the size of the dual port RAM in the micro controller code.\n
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ram8
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optionally specifies using an 8-bit RAM for the dual-port memory instantiation
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Note: This is the default
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ram32
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optionally specifies using a 32-bit RAM for the dual-port memory instantiation
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Note: This is required for Vivado 2013.3.\n
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Vivado Users:
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The peripheral creates a TCL script to facilitate turning the micro
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controller into an IP core. Look for a file with the name
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"vivado_<basePortName>.tcl".\n
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Example: The code fragments
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<addr> .outport(O_address) .inport(I_read)
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and
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<addr> .outport(O_address) <value> .outport(O_write)
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will read from and write to the dual-port RAM.\n
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Example: Function to read the byte at the specified address:
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; ( u_addr - u_value)
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.function als_read
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.outport(O_address) .inport(I_read) .return
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or
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; ( u_addr - u_value)
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.function als_read
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.outport(O_address) I_read .return(inport)
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To invoke the function:
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<addr> .call(als_read)
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or
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.call(als_read,<addr>)\n
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Example: Function to write the byte at the specified address:
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; ( u_value u_addr - )
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.function als_write
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.outport(O_address) O_write outport .return(drop)
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To invoke the function:
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<value> <addr> .call(als_write)
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or
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<value> .call(als_write,<addr>)\n
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Example: Spin on an address, waiting for the host processor to write to the
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address, do something when the address is written to, and then
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clear its contents.
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0x00 .outport(O_address)
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:loop .inport(I_read) 0= .jumpc(loop)
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; Avoid race conditions between the processor writes and the micro
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; controller read.
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.inport(I_read)
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...
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; clear the value and start waiting again
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0x00 O_address outport O_write outport .jump(loop,drop)\n
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LEGAL NOTICE: ARM has restrictions on what kinds of applications can use
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interfaces based on their AXI protocol. Ensure your application is in
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compliance with their restrictions before using this peripheral for an AXI
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interface.
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"""
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def __init__(self,peripheralFile,config,param_list,loc):
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# Use the externally provided file name for the peripheral
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self.peripheralFile = peripheralFile;
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# Get the parameters.
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allowables = (
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( 'address', r'O_\w+$', None, ),
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( 'basePortName', r'\w+$', None, ),
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( 'ram8', None, None, ),
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( 'ram32', None, None, ),
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( 'read', r'I_\w+$', None, ),
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( 'size', r'\S+$', lambda v : self.IntPow2Method(config,v,lowLimit=16,highLimit=256), ),
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( 'write', r'O_\w+$', None, ),
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);
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names = [a[0] for a in allowables];
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for param_tuple in param_list:
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param = param_tuple[0];
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if param not in names:
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raise SSBCCException('Unrecognized parameter "%s" at %s' % (param,loc,));
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param_test = allowables[names.index(param)];
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self.AddAttr(config,param,param_tuple[1],param_test[1],loc,param_test[2]);
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# Ensure the required parameters are provided.
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for paramname in (
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'address',
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'basePortName',
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'read',
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'write',
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):
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if not hasattr(self,paramname):
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raise SSBCCException('Required parameter "%s" is missing at %s' % (paramname,loc,));
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# Set optional parameters.
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for optionalpair in (
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('size', 256, ),
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):
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if not hasattr(self,optionalpair[0]):
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setattr(self,optionalpair[0],optionalpair[1]);
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# Ensure exclusive pair configurations are set and consistent.
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for exclusivepair in (
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('ram8','ram32','ram8',True,),
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):
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if hasattr(self,exclusivepair[0]) and hasattr(self,exclusivepair[1]):
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raise SSBCCException('Only one of "%s" and "%s" can be specified at %s' % (exclusivepair[0],exclusivepair[1],loc,));
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if not hasattr(self,exclusivepair[0]) and not hasattr(self,exclusivepair[1]):
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setattr(self,exclusivepair[2],exclusivepair[3]);
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# Set the string used to identify signals associated with this peripheral.
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self.namestring = self.basePortName;
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# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
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self.address_width = int(math.log(self.size,2));
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for signal in (
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( '%s_aresetn', 1, 'input', ),
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( '%s_aclk', 1, 'input', ),
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( '%s_awvalid', 1, 'input', ),
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( '%s_awready', 1, 'output', ),
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( '%s_awaddr', self.address_width, 'input', ),
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( '%s_wvalid', 1, 'input', ),
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( '%s_wready', 1, 'output', ),
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( '%s_wdata', 32, 'input', ),
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( '%s_wstrb', 4, 'input', ),
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( '%s_bresp', 2, 'output', ),
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( '%s_bvalid', 1, 'output', ),
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( '%s_bready', 1, 'input', ),
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( '%s_arvalid', 1, 'input', ),
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( '%s_arready', 1, 'output', ),
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( '%s_araddr', self.address_width, 'input', ),
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( '%s_rvalid', 1, 'output', ),
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( '%s_rready', 1, 'input', ),
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( '%s_rdata', 32, 'output', ),
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( '%s_rresp', 2, 'output', ),
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):
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thisName = signal[0] % self.basePortName;
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config.AddIO(thisName,signal[1],signal[2],loc);
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config.AddSignal('s__%s__mc_addr' % self.namestring, self.address_width, loc);
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config.AddSignal('s__%s__mc_rdata' % self.namestring, 8, loc);
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config.AddOutport((self.address,False,
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('s__%s__mc_addr' % self.namestring, self.address_width, 'data', ),
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),loc);
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config.AddInport((self.read,
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('s__%s__mc_rdata' % self.namestring, 8, 'data', ),
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),loc);
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self.ix_write = config.NOutports();
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config.AddOutport((self.write,False,
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# empty list
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),loc);
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# Add the 'clog2' function to the processor (if required).
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config.functions['clog2'] = True;
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def GenVerilog(self,fp,config):
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body = self.LoadCore(self.peripheralFile,'.v');
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for subpair in (
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( r'\bL__', 'L__@NAME@__', ),
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( r'\bgen__', 'gen__@NAME@__', ),
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( r'\bi_a', '@NAME@_a', ),
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( r'\bi_b', '@NAME@_b', ),
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( r'\bi_r', '@NAME@_r', ),
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( r'\bi_w', '@NAME@_w', ),
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( r'\bix__', 'ix__@NAME@__', ),
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( r'\bo_', '@NAME@_', ),
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( r'\bs__', 's__@NAME@__', ),
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( r'@IX_WRITE@', "8'h%02x" % self.ix_write, ),
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( r'@NAME@', self.namestring, ),
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( r'@SIZE@', str(self.size), ),
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( r'@MEM8@', '1' if hasattr(self,'mem8') else '0', ),
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):
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body = re.sub(subpair[0],subpair[1],body);
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body = self.GenVerilogFinal(config,body);
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fp.write(body);
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