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sinclairrf |
################################################################################
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#
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# Copyright 2012-2013, Sinclair R.F., Inc.
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#
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################################################################################
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import math;
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import re;
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from ssbccPeripheral import SSBCCperipheral
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from ssbccUtil import SSBCCException;
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class UART_Tx(SSBCCperipheral):
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"""
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Transmit side of a UART:
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1 start bit
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8 data bits
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1 or 2 stop bits\n
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Usage:
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PERIPHERAL UART_Tx outport=O_outport_name \\
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outstatus=I_outstatus_name \\
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baudmethod={clk/rate|count} \\
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[outsignal=o_name] \\
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[noOutFIFO|outFIFO=n] \\
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[nStop={1|2}]\n
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Where:
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outport=O_outport_name
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specifies the symbol used by the outport instruction to write a byte to
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the peripheral
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Note: The name must start with "O_".
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outstatus=I_outstatus_name
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specifies the symbol used by the inport instruction to get the status of
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the output side of the peripheral
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Note: The name must start with "I_".
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baudmethod
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specifies the method to generate the desired bit rate:
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1st method: clk/rate
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clk is the frequency of "i_clk" in Hz
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a number will be interpreted as the clock frequency in Hz
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a symbol will be interpreted as a parameter
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Note: this parameter must have been declared with a "PARAMETER"
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command
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rate is the desired baud rate
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this is specified as per "clk"
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2nd method:
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specify the number of "i_clk" clock cycles between bit edges
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Note: clk, rate, and count can be parameters or constants. For example,
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the following uses the parameter G_CLK_FREQ_HZ for the clock
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frequency and a hard-wired baud rate of 9600:
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"baudmethod=G_CLK_FREQ_HZ/9600".
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Note: The numeric values can have Verilog-style '_' separators between
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the digits. For example, 100_000_000 represents 100 million.
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outsignal=o_name
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optionally specifies the name of the output signal
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Default: o_UART_Tx
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noOutFIFO
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optionally state that the peripheral will not have an output FIFO
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Note: This is the default.
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outFIFO=n
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optionally add a FIFO of depth n to the output side of the UART
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Note: n must be a power of 2.
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nStop=n
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optionally configure the peripheral for n stop bits
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default: 1 stop bit
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Note: n must be 1 or 2
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Note: the peripheral does not accept 1.5 stop bits\n
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The following ports are provided by this peripheral:
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O_outport_name
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output the next 8-bit value to transmit or to queue for transmission
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Note: If there is no output FIFO or if there is an output FIFO and this
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write would cause a FIFO overflow, then this byte will be
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discarded.
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I_outstatus_name
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input the status of the output side of the peripheral
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bit 0: output busy
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this bit will be high when the output side of the peripheral cannot
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accept more writes
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Note: If there is no FIFO this means that the peripheral is still
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transmitting the last byte. If there is an output FIFO it means
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that it is full.\n
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Note: "Busy" is used rather that "ready" to facilitate loops that wait
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for a not-busy status to send the next byte. See the examples below.\n
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WARNING: The peripheral is very simple and does not protect against writing a
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new value in the middle of a transmition or writing to a full FIFO.
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Adding such logic would be contrary to the design principle of
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keeping the HDL small and relying on the assembly code to provide
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the protection.\n
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Example: Configure the UART for 115200 baud using a 100 MHz clock and
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transmit the message "Hello World!"\n
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Within the processor architecture file include the configuration command:\n
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PERIPHERAL UART_Tx O_UART_TX I_UART_TX baudmethod=100_000_000/115200\n
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Use the following assembly code to transmit the message "Hello World!".
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This transmits the entire message whether or not the peripheral has a FIFO.\n
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N"Hello World!\\r\\n"
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:loop .outport(O_UART_TX) :wait .inport(I_UART_TX_BUSY) .jumpc(wait) .jumpc(loop,nop) drop
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"""
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def __init__(self,peripheralFile,config,param_list,loc):
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# Use the externally provided file name for the peripheral
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self.peripheralFile = peripheralFile;
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# Get the parameters.
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for param_tuple in param_list:
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param = param_tuple[0];
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param_arg = param_tuple[1];
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for param_test in (
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('noOutFIFO', None, None, ),
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('nStop', r'[12]$', int, ),
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('outport', r'O_\w+$', None, ),
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('outsignal', r'o_\w+$', None, ),
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('outstatus', r'I_\w+$', None, ),
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):
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if param == param_test[0]:
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self.AddAttr(config,param,param_arg,param_test[1],loc,param_test[2]);
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break;
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else:
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if param == 'baudmethod':
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self.AddRateMethod(config,param,param_arg,loc);
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elif param in ('outFIFO',):
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self.AddAttr(config,param,param_arg,r'[1-9]\d*$',loc,int);
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x = getattr(self,param);
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if math.modf(math.log(x,2))[0] != 0:
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raise SSBCCException('%s=%d must be a power of 2 at %s' % (param,x,loc,));
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else:
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raise SSBCCException('Unrecognized parameter at %s: %s' % (loc,param,));
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# Ensure the required parameters are provided.
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for paramname in (
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'baudmethod',
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'outport',
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'outstatus',
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):
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if not hasattr(self,paramname):
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raise SSBCCException('Required parameter "%s" is missing at %s' % (paramname,loc,));
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# Set optional parameters.
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for optionalpair in (
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('nStop', 1, ),
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('outsignal', 'o_UART_Tx', ),
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):
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if not hasattr(self,optionalpair[0]):
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setattr(self,optionalpair[0],optionalpair[1]);
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# Ensure exclusive pair configurations are set and consistent.
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for exclusivepair in (
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('noOutFIFO', 'outFIFO', 'noOutFIFO', True, ),
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):
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if hasattr(self,exclusivepair[0]) and hasattr(self,exclusivepair[1]):
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raise SSBCCException('Only one of "%s" and "%s" can be specified at %s' % (exclusivepair[0],exclusivepair[1],loc,));
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if not hasattr(self,exclusivepair[0]) and not hasattr(self,exclusivepair[1]):
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setattr(self,exclusivepair[2],exclusivepair[3]);
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if hasattr(self,exclusivepair[0]):
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delattr(self,exclusivepair[0]);
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setattr(self,exclusivepair[1],0);
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# Set the string used to identify signals associated with this peripheral.
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self.namestring = self.outsignal;
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# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
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config.AddIO(self.outsignal,1,'output',loc);
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config.AddSignal('s__%s__Tx' % self.namestring,8,loc);
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config.AddSignal('s__%s__Tx_busy' % self.namestring,1,loc);
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config.AddSignal('s__%s__Tx_wr' % self.namestring,1,loc);
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config.AddOutport((self.outport,False,
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('s__%s__Tx' % self.namestring,8,'data',),
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('s__%s__Tx_wr' % self.namestring,1,'strobe',),
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),loc);
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config.AddInport((self.outstatus,
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('s__%s__Tx_busy' % self.namestring,1,'data',),
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),loc);
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# Add the 'clog2' function to the processor (if required).
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config.functions['clog2'] = True;
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def GenVerilog(self,fp,config):
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for bodyextension in ('.v',):
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body = self.LoadCore(self.peripheralFile,bodyextension);
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for subpair in (
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(r'\bL__', 'L__@NAME@__', ),
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(r'\bgen__', 'gen__@NAME@__', ),
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(r'\bs__', 's__@NAME@__', ),
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(r'@BAUDMETHOD@', str(self.baudmethod), ),
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(r'@NSTOP@', str(self.nStop), ),
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(r'@OUTFIFO@', str(self.outFIFO), ),
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(r'@NAME@', self.namestring, ),
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):
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body = re.sub(subpair[0],subpair[1],body);
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body = self.GenVerilogFinal(config,body);
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fp.write(body);
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