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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [UART_Tx.v] - Blame information for rev 9

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1 2 sinclairrf 
//
2 
// PERIPHERAL UART_Tx:  @NAME@
3 9 sinclairrf 
// Copyright 2013-2015 Sinclair R.F., Inc.
4 2 sinclairrf 
//
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localparam L__OUTFIFO_NBITS = $clog2(@OUTFIFO@);
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localparam L__COUNT         = @BAUDMETHOD@-1;
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localparam L__COUNT_NBITS   = $clog2(L__COUNT+1);
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localparam L__NTX           = 1+8+@NSTOP@-1;
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localparam L__NTX_NBITS     = $clog2((L__NTX==0)?1:L__NTX);
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generate
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reg  [7:0] s__Tx_data;
12 6 sinclairrf 
wire       s__Tx_enabled = @ENABLED@;
13 2 sinclairrf 
reg        s__Tx_go;
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reg        s__Tx_uart_busy;
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if (@OUTFIFO@ == 0) begin : gen__nooutfifo
16 9 sinclairrf 
  always @ (s__Tx_uart_busy, s__Tx_enabled)
17 6 sinclairrf 
    s__Tx_busy = s__Tx_uart_busy || !s__Tx_enabled;
18 2 sinclairrf 
  always @ (s__Tx)
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    s__Tx_data = s__Tx;
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  always @ (s__Tx_wr)
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    s__Tx_go = s__Tx_wr;
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end else begin : gen__outfifo
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  reg [7:0] s__Tx_fifo_mem[@OUTFIFO@-1:0];
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  reg [L__OUTFIFO_NBITS:0] s__Tx_fifo_addr_in = {(L__OUTFIFO_NBITS+1){1'b0}};
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  always @ (posedge i_clk)
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    if (i_rst)
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      s__Tx_fifo_addr_in <= {(L__OUTFIFO_NBITS+1){1'b0}};
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    else if (s__Tx_wr) begin
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      s__Tx_fifo_addr_in <= s__Tx_fifo_addr_in + { {(L__OUTFIFO_NBITS){1'b0}}, 1'b1 };
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      s__Tx_fifo_mem[s__Tx_fifo_addr_in[0+:L__OUTFIFO_NBITS]] <= s__Tx;
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    end else
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      s__Tx_fifo_addr_in <= s__Tx_fifo_addr_in;
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  reg [L__OUTFIFO_NBITS:0] s__Tx_fifo_addr_out;
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  reg s__Tx_fifo_has_data = 1'b0;
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  reg s__Tx_fifo_full = 1'b0;
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  always @ (posedge i_clk)
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    if (i_rst) begin
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      s__Tx_fifo_has_data <= 1'b0;
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      s__Tx_fifo_full <= 1'b0;
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    end else begin
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      s__Tx_fifo_has_data <= (s__Tx_fifo_addr_out != s__Tx_fifo_addr_in);
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      s__Tx_fifo_full <= (s__Tx_fifo_addr_out == (s__Tx_fifo_addr_in ^ { 1'b1, {(L__OUTFIFO_NBITS){1'b0}} }));
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    end
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  initial s__Tx_go = 1'b0;
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  always @ (posedge i_clk)
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    if (i_rst)
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      s__Tx_go <= 1'b0;
48 6 sinclairrf 
    else if (s__Tx_enabled && s__Tx_fifo_has_data && !s__Tx_uart_busy && !s__Tx_go)
49 2 sinclairrf 
      s__Tx_go <= 1'b1;
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    else
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      s__Tx_go <= 1'b0;
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  initial s__Tx_fifo_addr_out = {(L__OUTFIFO_NBITS+1){1'b0}};
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  always @ (posedge i_clk)
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    if (i_rst)
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      s__Tx_fifo_addr_out <= {(L__OUTFIFO_NBITS+1){1'b0}};
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    else if (s__Tx_go)
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      s__Tx_fifo_addr_out <= s__Tx_fifo_addr_out + { {(L__OUTFIFO_NBITS){1'b0}}, 1'b1 };
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    else
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      s__Tx_fifo_addr_out <= s__Tx_fifo_addr_out;
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  initial s__Tx_data = 8'd0;
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  always @ (posedge i_clk)
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    if (i_rst)
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      s__Tx_data <= 8'd0;
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    else
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      s__Tx_data <= s__Tx_fifo_mem[s__Tx_fifo_addr_out[0+:L__OUTFIFO_NBITS]];
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  always @ (s__Tx_fifo_full)
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    s__Tx_busy = s__Tx_fifo_full;
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end
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// Count the clock cycles to decimate to the desired baud rate.
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reg [L__COUNT_NBITS-1:0] s__Tx_count = {(L__COUNT_NBITS){1'b0}};
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reg s__Tx_count_is_zero = 1'b0;
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always @ (posedge i_clk)
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  if (i_rst) begin
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    s__Tx_count <= {(L__COUNT_NBITS){1'b0}};
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    s__Tx_count_is_zero <= 1'b0;
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  end else if (s__Tx_go || s__Tx_count_is_zero) begin
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    s__Tx_count <= L__COUNT[0+:L__COUNT_NBITS];
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    s__Tx_count_is_zero <= 1'b0;
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  end else begin
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    s__Tx_count <= s__Tx_count - { {(L__COUNT_NBITS-1){1'b0}}, 1'b1 };
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    s__Tx_count_is_zero <= (s__Tx_count == { {(L__COUNT_NBITS-1){1'b0}}, 1'b1 });
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  end
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// Latch the bits to output.
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reg [7:0] s__Tx_stream = 8'hFF;
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always @ (posedge i_clk)
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  if (i_rst)
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    s__Tx_stream <= 8'hFF;
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  else if (s__Tx_go)
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    s__Tx_stream <= s__Tx_data;
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  else if (s__Tx_count_is_zero)
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    s__Tx_stream <= { 1'b1, s__Tx_stream[1+:7] };
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  else
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    s__Tx_stream <= s__Tx_stream;
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// Generate the output bit stream.
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initial @NAME@ = 1'b1;
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always @ (posedge i_clk)
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  if (i_rst)
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    @NAME@ <= 1'b1;
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  else if (s__Tx_go)
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    @NAME@ <= 1'b0;
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  else if (s__Tx_count_is_zero)
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    @NAME@ <= s__Tx_stream[0];
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  else
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    @NAME@ <= @NAME@;
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// Count down the number of bits.
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reg [L__NTX_NBITS-1:0] s__Tx_n = {(L__NTX_NBITS){1'b0}};
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always @ (posedge i_clk)
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  if (i_rst)
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    s__Tx_n <= {(L__NTX_NBITS){1'b0}};
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  else if (s__Tx_go)
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    s__Tx_n <= L__NTX[0+:L__NTX_NBITS];
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  else if (s__Tx_count_is_zero)
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    s__Tx_n <= s__Tx_n - { {(L__NTX_NBITS-1){1'b0}}, 1'b1 };
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  else
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    s__Tx_n <= s__Tx_n;
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// The status bit is 1 if the core is busy and 0 otherwise.
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initial s__Tx_uart_busy = 1'b1;
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always @ (posedge i_clk)
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  if (i_rst)
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    s__Tx_uart_busy <= 1'b0;
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  else if (s__Tx_go)
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    s__Tx_uart_busy <= 1'b1;
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  else if (s__Tx_count_is_zero && (s__Tx_n == {(L__NTX_NBITS){1'b0}}))
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    s__Tx_uart_busy <= 1'b0;
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  else
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    s__Tx_uart_busy <= s__Tx_uart_busy;
127 
endgenerate

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