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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [adder_16bit.py] - Blame information for rev 10

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1 2 sinclairrf
################################################################################
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#
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# Copyright 2012-2013, Sinclair R.F., Inc.
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#
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################################################################################
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from ssbccPeripheral import SSBCCperipheral
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class adder_16bit(SSBCCperipheral):
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  """The "adder_16bit" peripheral adds or subtracts two 16 bit values.\n
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Usage:
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  PERIPHERAL adder_16bit\n
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The following OUTPORTs are provided by the peripheral:
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  port                description
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  O_ADDER_16BIT_MSB1  MSB of first argument
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  O_ADDER_16BIT_LSB1  LSB of first argument
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  O_ADDER_16BIT_MSB2  MSB of second argument
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  O_ADDER_16BIT_LSB2  LSB of second argument
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  O_ADDER_16BIT_OP    0 ==> add, 1 ==> subtract\n
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The following INPORTs are provided by the peripheral:
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  port                description
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  I_ADDER_16BIT_MSB   MSB of the sum/difference
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  I_ADDER_16BIT_LSB   LSB of the sum/difference\n
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Example:  Incorporate the peripheral:\n
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Example:  Add an 8-bit value and a 16-bit value from the stack:\n
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  Within the processor architecture file include the configuration command:\n
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  PERIPHERAL adder_16bit\n
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  Use the following assembly code to perform the addition to implement a
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  function that adds an 8-bit value at the top of the data stack to the 16-bit
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  value immediately below it:\n
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  ; ( u2_LSB u2_MSB u1 - (u1+u2)_LSB (u1+u2)_MSB
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  .function add_u8_u16__u16
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    ; write the 8-bit value to the peripheral (after converting it to a 16 bit
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    ; value)
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    ; write the 16-bit value to the peripheral
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    .outport(O_ADDER_16BIT_MSB2) .outport(O_ADDER_16BIT_LSB2)
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    ; command an addition
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    ; push the 16-bit sum onto the stack
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    .inport(I_ADDER_16BIT_LSB) .inport(I_ADDER_16BIT_MSB)
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  .return
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"""
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  def __init__(self,peripheralFile,config,params,loc):
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    # Use the externally provided file name for the peripheral
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    self.peripheralFile = peripheralFile;
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    # List the signals to be declared for the peripheral.
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    config.AddSignal('s__adder_16bit_out_MSB',8,loc);
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    config.AddSignal('s__adder_16bit_out_LSB',8,loc);
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    config.AddSignal('s__adder_16bit_in_MSB1',8,loc);
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    config.AddSignal('s__adder_16bit_in_LSB1',8,loc);
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    config.AddSignal('s__adder_16bit_in_MSB2',8,loc);
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    config.AddSignal('s__adder_16bit_in_LSB2',8,loc);
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    config.AddSignal('s__adder_16bit_in_op',1,loc);
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    # List the input ports to the peripheral.
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    config.AddInport(('I_ADDER_16BIT_MSB',
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                     ('s__adder_16bit_out_MSB',8,'data',),
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                    ),loc);
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    config.AddInport(('I_ADDER_16BIT_LSB',
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                     ('s__adder_16bit_out_LSB',8,'data',),
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                    ),loc);
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    # List the output ports from the peripheral.
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    config.AddOutport(('O_ADDER_16BIT_MSB1',False,
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                       ('s__adder_16bit_in_MSB1',8,'data',),
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                     ),loc);
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    config.AddOutport(('O_ADDER_16BIT_LSB1',False,
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                      ('s__adder_16bit_in_LSB1',8,'data',),
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                     ),loc);
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    config.AddOutport(('O_ADDER_16BIT_MSB2',False,
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                      ('s__adder_16bit_in_MSB2',8,'data',),
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                     ),loc);
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    config.AddOutport(('O_ADDER_16BIT_LSB2',False,
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                      ('s__adder_16bit_in_LSB2',8,'data',),
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                     ),loc);
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    config.AddOutport(('O_ADDER_16BIT_OP',False,
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                      ('s__adder_16bit_in_op',1,'data',),
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                     ),loc);
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  def GenAssembly(self,config):
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    fp = file('adder_16bit.s','w');
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    fp.write("""; Copyright 2012-2013, Sinclair R.F., Inc.
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; adder_16bit.s
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; library to facilitate using the 16-bit adder peripheral
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; ( u_1_LSB u_1_MSB u_2_LSB u_2_MSB u_op - (u_1+u_2)_LSB (u_1+u_2)_MSB )
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.function addsub_u16_u16__u16
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  .outport(O_ADDER_16BIT_OP)
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  .outport(O_ADDER_16BIT_MSB2) .outport(O_ADDER_16BIT_LSB2)
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  .outport(O_ADDER_16BIT_MSB1) .outport(O_ADDER_16BIT_LSB1)
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  .inport(I_ADDER_16BIT_LSB) I_ADDER_16BIT_MSB
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.return(inport)
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""");
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  def GenVerilog(self,fp,config):
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    body = """//
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// PERIPHERAL adder_16bit:
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//
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always @ (posedge i_clk)
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  if (s__adder_16bit_in_op == 1\'b0)
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    { s__adder_16bit_out_MSB, s__adder_16bit_out_LSB }
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      <= { s__adder_16bit_in_MSB1, s__adder_16bit_in_LSB1 }
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       + { s__adder_16bit_in_MSB2, s__adder_16bit_in_LSB2 };
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  else
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    { s__adder_16bit_out_MSB, s__adder_16bit_out_LSB }
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      <= { s__adder_16bit_in_MSB1, s__adder_16bit_in_LSB1 }
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       - { s__adder_16bit_in_MSB2, s__adder_16bit_in_LSB2 };
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""";
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    body = self.GenVerilogFinal(config,body);
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    fp.write(body);

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