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sinclairrf |
################################################################################
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#
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# Copyright 2013, Sinclair R.F., Inc.
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#
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################################################################################
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import re;
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from ssbccPeripheral import SSBCCperipheral
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from ssbccUtil import SSBCCException;
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class big_inport(SSBCCperipheral):
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"""
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Shift two or more writes to a single OUTPORT to construct a wide output
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signal.\n
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Usage:
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PERIPHERAL big_inport \\
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outlatch=O_name \\
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inport=I_name \\
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insignal=i_name \\
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width=<N>\n
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Where:
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outlatch=O_name
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specifies the symbol used to latch the incoming value
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inport=I_name
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specifies the symbol used to read from the output port
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insignal=i_name
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specifies the name of the signal input to the module
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width=<N>
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specifies the width of the I/O register\n
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Example: Create a 23-bit input signal to receive an external (synchronous)
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counter.\n
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PORTCOMMENT 23-bit counter
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PERIPHERAL big_inport \\
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outlatch=O_LATCH_COUNTER \\
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inport=I_COUNTER \\
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insignal=i_counter \\
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width=23\n
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Reading the counter requires issuing a command to latch the current value and
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then 3 reads to the I/O port as follows:\n
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; Latch the external counter.
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.outstrobe(O_LATCH_COUNTER)
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; Read the 3-byte value of the count
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; ( - u_LSB u u_MSB )
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.inport(I_COUNTER)
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.inport(I_COUNTER)
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.inport(I_COUNTER)
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"""
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def __init__(self,peripheralFile,config,param_list,loc):
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# Get the parameters.
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allowables = (
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('outlatch', r'O_\w+$', None, ),
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('inport', r'I_\w+$', None, ),
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('insignal', r'i_\w+$', None, ),
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('width', r'(9|[1-9]\d*)$', int, ),
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);
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names = [a[0] for a in allowables];
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for param_tuple in param_list:
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param = param_tuple[0];
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if param not in names:
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raise SSBCCException('Unrecognized parameter "%s" at %s' % (param,loc,));
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param_test = allowables[names.index(param)];
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self.AddAttr(config,param,param_tuple[1],param_test[1],loc,param_test[2]);
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# Ensure the required parameters are provided (all parameters are required).
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for paramname in names:
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if not hasattr(self,paramname):
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raise SSBCCException('Required parameter "%s" is missing at %s' % (paramname,loc,));
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# There are no optional parameters.
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# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
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config.AddIO(self.insignal,self.width,'input',loc);
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config.AddSignal('s__%s__inport' % self.insignal, self.width, loc);
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self.ix_latch = config.NOutports();
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config.AddOutport((self.outlatch,True,
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# empty list
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),loc);
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self.ix_inport = config.NInports();
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config.AddInport((self.inport,
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('s__%s__inport' % self.insignal, self.width, 'data', ),
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),loc);
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def GenVerilog(self,fp,config):
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body = """//
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// PERIPHERAL big_inport: @INSIGNAL@
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//
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always @ (posedge i_clk)
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if (i_rst)
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@NAME@ <= @WIDTH@'d0;
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else if (s_outport && (s_T == @IX_LATCH@))
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@NAME@ <= @INSIGNAL@;
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else if (s_inport && (s_T == @IX_INPORT@))
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@NAME@ <= { 8'd0, @NAME@[@WIDTH-1:8@] };
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else
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@NAME@ <= @NAME@;
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"""
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for subpair in (
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(r'@IX_LATCH@', "8'd%d" % self.ix_latch, ),
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(r'@IX_INPORT@', "8'd%d" % self.ix_inport, ),
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(r'@WIDTH@', str(self.width), ),
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(r'@WIDTH-1:8@', '%d:8' % (self.width-1) if self.width > 9 else '8' ),
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(r'@NAME@', 's__@INSIGNAL@__inport', ),
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(r'@INSIGNAL@', self.insignal, ),
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):
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body = re.sub(subpair[0],subpair[1],body);
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body = self.GenVerilogFinal(config,body);
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fp.write(body);
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