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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [counter.py] - Blame information for rev 6

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################################################################################
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#
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# Copyright 2013-2014, Sinclair R.F., Inc.
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#
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################################################################################
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import re;
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from ssbccPeripheral import SSBCCperipheral
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from ssbccUtil import SSBCCException;
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class counter(SSBCCperipheral):
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  """
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  Count received strobes.\n
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  Usage:
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    PERIPHERAL counter \\
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                        insignal=i_name \\
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                        inport=I_NAME \\
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                        [width=<N> outlatch=O_NAME]\n
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  Where:
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    insignal=i_name
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      specifies the name of the signal input to the micro controller
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    input=I_NAME
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      specifies the symbol use to read the count
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    width=<N>
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      optionally specifies the width of the counter
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      Note:  The default is 8 bits.
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      Note:  If the width is more than 8 bits then the optional outlatch needs
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             to be provided.  This is strobe outport is used to latch the value
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             of the counter so that it can be input from its LSB to its MSB.\n
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  Note:  The counter is not cleared when it is read.  Software must maintain the
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         previous value of the count if delta-counts are required.\n
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  Example:  Create an 8-bit count for the number of strobe events received.\n
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    PORTCOMMENT external strobe (input to 8-bit counter)
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    PERIPHERAL counter \\
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                        insignal=i_strobe \\
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                        inport=I_STROBE_COUNT\n
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  Read the count:\n
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    .inport(I_STROBE_COUNT)\n
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  Example:  Create a 12-bit count for the number of strobe events received.\n
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    PORTCOMMENT external strobe (input to 12-bit counter)
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    PERIPHERAL counter \\
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                        insignal=i_strobe \\
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                        inport=I_STROBE_COUNT \\
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                        width=12 \\
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                        outlatch=O_LATCH_STROBE_COUNT\n
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  Read the count:
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    ; latch the count
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    .outstrobe(O_LATCH_STROBE_COUNT)
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    ; read the count LSB first
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    ; ( - u_LSB u_MSB )
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    .inport(I_STROBE_COUNT) .inport(I_STROBE_COUNT)
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  """
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  def __init__(self,peripheralFile,config,param_list,loc):
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    # Use the externally provided file name for the peripheral
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    self.peripheralFile = peripheralFile;
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    # Get the parameters.
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    allowables = (
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      ( 'outlatch',     r'O_\w+$',              None,   ),
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      ( 'inport',       r'I_\w+$',              None,   ),
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      ( 'insignal',     r'i_\w+$',              None,   ),
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      ( 'width',        r'(9|[1-9]\d*)$',       int,    ),
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    );
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    names = [a[0] for a in allowables];
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    for param_tuple in param_list:
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      param = param_tuple[0];
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      if param not in names:
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        raise SSBCCException('Unrecognized parameter "%s" at %s' % (param,loc,));
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      param_test = allowables[names.index(param)];
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      self.AddAttr(config,param,param_tuple[1],param_test[1],loc,param_test[2]);
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    # Ensure the optional width is set.
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    if not hasattr(self,'width'):
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      self.width=8;
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    # Ensure the required parameters are provided.
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    required = ['inport','insignal',];
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    if self.width > 8:
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      required.append('outlatch');
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    for paramname in required:
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      if not hasattr(self,paramname):
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        raise SSBCCException('Required parameter "%s" is missing at %s' % (paramname,loc,));
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    # There are no optional parameters.
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    # Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
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    config.AddIO(self.insignal,1,'input',loc);
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    config.AddSignal('s__%s__inport' % self.insignal, self.width, loc);
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    self.ix_inport = config.NInports();
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    config.AddInport((self.inport,
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                      ('s__%s__inport' % self.insignal, self.width, 'data', ),
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                      ),loc);
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    self.ix_latch = config.NOutports();
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    if hasattr(self,'outlatch'):
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      config.AddOutport((self.outlatch,True,
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                        # empty list
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                        ),loc);
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  def GenVerilog(self,fp,config):
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    if self.width <= 8:
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      body = """//
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// PERIPHERAL counter:  @INSIGNAL@
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//
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always @ (posedge i_clk)
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  if (i_rst)
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    @NAME@ <= @WIDTH@'d0;
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  else if (@INSIGNAL@)
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    @NAME@ <= @NAME@ + @WIDTH@'d1;
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  else
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    @NAME@ <= @NAME@;
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""";
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    else:
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      body = """//
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// PERIPHERAL counter:  @INSIGNAL@
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//
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reg [@WIDTH-1@:0] s__count = @WIDTH@'d0;
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always @ (posedge i_clk)
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  if (i_rst)
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    s__count <= @WIDTH@'d0;
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  else if (@INSIGNAL@)
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    s__count <= s__count + @WIDTH@'d1;
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  else
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    s__count <= s__count;
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always @ (posedge i_clk)
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  if (i_rst)
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    @NAME@ <= @WIDTH@'d0;
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  else if (s_outport && (s_T == @IX_LATCH@))
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    @NAME@ <= s__count;
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  else if (s_inport && (s_T == @IX_INPORT@))
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    @NAME@ <= { 8'd0, @NAME@[@WIDTH-1:8@] };
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  else
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    @NAME@ <= @NAME@;
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""";
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    for subpair in (
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        ( r'\bs__',       's__@NAME@__',                                          ),
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        ( r'@IX_LATCH@',  "8'd%d" % self.ix_latch,                                ),
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        ( r'@IX_INPORT@', "8'd%d" % self.ix_inport,                               ),
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        ( r'@WIDTH@',     str(self.width),                                        ),
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        ( r'@WIDTH-1@',   str(self.width-1),                                      ),
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        ( r'@WIDTH-1:8@', '%d:8' % (self.width-1) if self.width > 9 else '8'      ),
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        ( r'@NAME@',      's__@INSIGNAL@__inport',                                ),
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        ( r'@INSIGNAL@',  self.insignal,                                          ),
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      ):
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      body = re.sub(subpair[0],subpair[1],body);
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    body = self.GenVerilogFinal(config,body);
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    fp.write(body);

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