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sinclairrf |
################################################################################
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#
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# Copyright 2015, Sinclair R.F., Inc.
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#
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################################################################################
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from ssbccPeripheral import SSBCCinterruptPeripheral
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from ssbccUtil import SSBCCException
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class interrupt(SSBCCinterruptPeripheral):
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"""
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Interrupt peripheral for 1 to 8 interrupt inputs.\n
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This implements a variable-width interrupt input of up to 8 bits and
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generates an interrupt when one of these goes from low to high, provided that
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an interrupt is not already in progress.\n
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Usage:
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PERIPHERAL interrupt insignal<N>=[!]{i_name|s__name}[,C_NAME] \\
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[inport=I_NAME] \\
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[outmaskport=O_NAME] \\
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[inmaskport=I_NAME] \\
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[initmask=<value>]\n
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Where:
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insignal<N>={i_name|s__name}[,C_NAME]
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specifies one of the eight possible single-bit signal that will trigger
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the interrupt and optionally specify a constant defined by the interrupt
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bit position
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Note: Replace <N> with 0, 1, ..., 7
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Note: If the signal name starts with "i_" it will be added as a single
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bit wide input to the processor. If the signal name starts with
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"s__" it must be a signal from another peripheral with the given
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name.
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Note: If the signal name is preceded by a an exclamation mark, i.e., a
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"!", then the signal will be treated as falling-edge triggered
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instead of rising edge triggered.
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Note: External signals may need to be synchronized to the micro
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controller clock.
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inport=I_NAME
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provide the input port name to read the interrupt signal
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Note: This port is prohibited if there is only one interrupt signal and
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it is required if there is more than one interrupt signal.
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outmaskport=O_NAME
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optionally specifies a port to provide an enable/disable mask to
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the interrupt signals
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inmaskport=I_NAME
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optionally specifies a port to read the current enable/disable mask
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Note: This cannot be used if outmaskport is not specified.
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initmask=<value>
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optionally specifies the initial value of the mask
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Note: This cannot be used if outmaskport is not specified.
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Note: The value is either a Verilog format value or a decimal value.
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Note: If this is not specified then all interrupt bits will be enabled.\n
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Example: Trigger an interrupt when a 1 clock wide strobe is received from an
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external timer.\n
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# In the architecture file
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PERIPHERAL interrupt insignal0=i_timer_strobe\n
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; In the assembly file
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.interrupt
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; Do the timer event.
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...
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; Return from the interrupt.
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.returni\n
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Example: Monitor an external timer strobe and a FIFO empty flag (which is
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high when the FIFO is empty).\n
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# In the architecture file
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PERIPHERAL outFIFO_async data=o_fifo ... outempty=I_EMPTY
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PERIPHERAL interrupt insignal0=!s__o_fifo__outempty_in,C_INTERRUPT_MASK_FIFO \\
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insignal1=i_timer_strobe,C_INTERRUPT_MASK_TIMER \\
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inport=I_INTERRUPT\n
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; In the assembly file
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.interrupt
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; Read the interrupt condition.
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.inport(I_INTERRUPT)
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; If the interrupt was triggered by the timer, then handle the
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; timer event (but don't throw away the rest of the interrupt
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; condition).
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dup C_INTERRUPT_MASK_TIMER & .callc(...)
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; If the interrupt was triggered by the FIFO becoming empty, then
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; do whatever's appropriate (and throw away the interrupt
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; condition).
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C_INTERRUPT_MASK_FIFO & .callc(...)
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; Return from the interrupt.
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.returni\n
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WARNING: Setting the interrupt mask does not disable interrupts occuring
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before a bit in the mask is cleared. I.e., if a particular
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interrupt bit is disabled by a new interrupt mask, but an interrupt
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for that bit occured before the mask bit was cleared, then that
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interrupt bit will still have caused a pending interrupt. This is
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particularly important when the processor is starting.\n
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This can be resolved in part by using the following code at the top
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of the interrupt handler:\n
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.inport(I_INTERRUPT) .inport(I_INTERRUPT_MASK) &
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where .inport(I_INTERRUPT) gets the interrupt event(s) and
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.inport(I_INTERRUPT_MASK) gets the current interrupt mask.
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"""
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def __init__(self,peripheralFile,config,param_list,loc):
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"""
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Configure this peripheral as an interrupt peripheral.
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"""
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# Invoke the base class __init__ function before doing anything else.
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SSBCCinterruptPeripheral.__init__(self,config,loc)
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# Use the externally provided file name for the peripheral
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self.peripheralFile = peripheralFile
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# Get the parameters.
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allowables = (
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( 'initmask', r'\S+$', lambda v : self.IntValueMethod(v), ),
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( 'inmaskport', r'I_\w+$', None, ),
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( 'inport', r'I_\w+$', None, ),
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( 'outmaskport', r'O_\w+$', None, ),
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)
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names = [a[0] for a in allowables]
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self.insignal = [None for ix in range(config.Get('data_width'))]
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self.invert = 0
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for param_tuple in param_list:
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param = param_tuple[0]
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if re.match(r'insignal[0-7]$',param):
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if param_tuple[1] == None:
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raise SSBCCException('"%s" missing value at %s' % (param,loc,))
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ix = int(param[-1])
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if self.insignal[ix]:
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raise SSBCCException('%s already specified at %s' % (param,loc,))
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pars = re.findall(r'(!?)(i_\w+|s__\w+)(,C_\w+)?$',param_tuple[1])
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if not pars or not pars[0][1]:
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raise SSBCCException('I/O symbol at %s does not match required format "[!]{i_name|s__name}[,C_name]": "%s"' % (loc,param_tuple[1],))
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pars = pars[0]
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if pars[0]:
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self.invert |= 2**ix
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self.insignal[ix] = pars[1]
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if pars[2]:
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config.AddConstant(pars[2][1:],2**ix,loc)
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elif param in names:
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param_test = allowables[names.index(param)]
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self.AddAttr(config,param,param_tuple[1],param_test[1],loc,param_test[2])
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else:
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raise SSBCCException('Unrecognized parameter "%s" at %s' % (param,loc,))
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# Ensure the required parameters are set.
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if not any(self.insignal):
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raise SSBCCException('Required parameter insignal<N> missing at %s' % loc)
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self.width = sum(1 for ix in range(len(self.insignal)) if self.insignal[ix])
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ixMissing = [ix for ix in range(self.width) if not self.insignal[ix]]
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if ixMissing:
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raise SSBCCException('insignal%d missing at %s' % (ixMissing[0],loc,))
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if self.width == 1:
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if hasattr(self,'inport'):
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raise SSBCCException('Parameter "inport" is prohibited when there is only one interrupt signal at %s' % loc)
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else:
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if not hasattr(self,'inport'):
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raise SSBCCException('Required parameter "%s" is missing at %s' % (paramname,loc,))
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# Ensure optional parameters are consistent.
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for opt in ('inmaskport','initmask',):
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if hasattr(self,opt) and not hasattr(self,'outmaskport'):
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raise SSBCCException('Optional parameter "%s" requires "outmaskport" at %s' % (opt,loc,))
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if hasattr(self,'initmask'):
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if self.initmask >= 2**self.width:
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raise SSBCCException('Value of "initmask" exceeds interrupt width at %s' % loc)
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# Create the signal for the triggering interrupt source.
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config.AddSignal('s_interrupt_trigger',self.width,loc)
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# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
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for ix in [ix for ix in range(self.width) if re.match(r'i_',self.insignal[ix])]:
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config.AddIO(self.insignal[ix],1,'input',loc)
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if hasattr(self,'inport'):
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self.ix_inport = config.NInports()
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config.AddInport((self.inport,
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('s_interrupt_trigger',self.width,'data',),
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),
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loc)
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if not hasattr(self,'initmask'):
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self.initmask= '%d\'h%X' % (self.width,2**self.width-1,)
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if hasattr(self,'outmaskport'):
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self.masksignal = 's_interrupt_mask'
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config.AddSignalWithInit(self.masksignal,self.width,None,loc)
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config.AddOutport((self.outmaskport,False,
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(self.masksignal,self.width,'data',self.initmask,),
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),
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loc)
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if hasattr(self,'inmaskport'):
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config.AddInport((self.inmaskport,
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(self.masksignal,self.width,'data',),
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),
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loc)
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else:
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self.masksignal = self.initmask
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def GenVerilog(self,fp,config):
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body = self.LoadCore(self.peripheralFile,'.v');
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if self.width == 1:
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body = re.sub(r'reg s_interrupt_trigger_any.*?\n','',body);
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while re.search(r' {4,}s_interrupt_trigger_any',body):
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body = re.sub(r' {4,}s_interrupt_trigger_any.*?\n','',body);
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body = re.sub(r's_interrupt_trigger_any','s_interrupt_trigger',body);
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if not hasattr(self,'inport'):
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clear_trigger = 's_interrupt';
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else:
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clear_trigger = 's_inport && (s_T == %d)' % self.ix_inport;
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for subpair in (
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( r'@CLEAR_TRIGGER@', clear_trigger, ),
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( r'@IX_OUTPORT_DIS@', '8\'h%02X' % self.ix_outport_interrupt_dis, ),
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( r'@IX_OUTPORT_ENA@', '8\'h%02X' % self.ix_outport_interrupt_ena, ),
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( r'@INSIGNAL@', '{ %s }' % ', '.join(self.insignal[ix] for ix in range(self.width-1,-1,-1)), ),
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( r'@INVERT@', '%d\'h%X' % (self.width,self.invert,), ),
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( r'@MASK@', self.masksignal, ),
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( r'@WIDTH@ ', '' if self.width==1 else '[%d:0] ' % (self.width-1,), ),
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( r'@ZERO@', '%d\'h0' % self.width, ),
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):
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body = re.sub(subpair[0],subpair[1],body);
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body = self.GenVerilogFinal(config,body);
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fp.write(body);
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