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https://opencores.org/ocsvn/ssbcc/ssbcc/trunk
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sinclairrf |
//
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// PERIPHERAL interrupt
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// Copyright 2015, Sinclair R.F., Inc.
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//
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reg s_in_jump = 1'b0;
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always @ (posedge i_clk)
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if (i_rst)
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s_in_jump <= 1'b0;
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else
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s_in_jump <= (s_bus_pc == C_BUS_PC_JUMP) || (s_bus_pc == C_BUS_PC_RETURN);
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wire @WIDTH@ s_interrupt_raw = ( @INVERT@ ^ @INSIGNAL@ ) & @MASK@;
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reg @WIDTH@ s_interrupt_raw_s = @INVERT@;
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always @ (posedge i_clk)
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if (i_rst)
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s_interrupt_raw_s <= @INVERT@;
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else
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s_interrupt_raw_s <= s_interrupt_raw;
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wire @WIDTH@ s_interrupt_trigger_raw = s_interrupt_raw & ~s_interrupt_raw_s;
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reg s_interrupt_trigger_any = 1'b0;
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always @ (posedge i_clk)
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if (i_rst) begin
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s_interrupt_trigger <= @ZERO@;
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s_interrupt_trigger_any <= 1'b0;
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end else if (@CLEAR_TRIGGER@) begin
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s_interrupt_trigger <= s_interrupt_trigger_raw;
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s_interrupt_trigger_any <= |s_interrupt_trigger_raw;
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end else begin
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s_interrupt_trigger <= s_interrupt_trigger | s_interrupt_trigger_raw;
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s_interrupt_trigger_any <= s_interrupt_trigger_any || (|s_interrupt_trigger_raw);
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end
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reg s_interrupt_ena;
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always @ (*)
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s_interrupt = s_interrupt_ena && s_interrupt_trigger_any && ~s_in_jump;
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always @ (posedge i_clk)
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if (i_rst)
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s_interrupted <= 1'b0;
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else
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s_interrupted <= s_interrupt;
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initial s_interrupt_ena = 1'b0;
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always @ (posedge i_clk)
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if (i_rst)
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s_interrupt_ena <= 1'b0;
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else if (s_interrupt)
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s_interrupt_ena <= 1'b0;
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else if (s_outport && (s_T == @IX_OUTPORT_ENA@))
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s_interrupt_ena <= 1'b1;
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else if (s_outport && (s_T == @IX_OUTPORT_DIS@))
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s_interrupt_ena <= 1'b0;
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else
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s_interrupt_ena <= s_interrupt_ena;
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